Added coherence message type enums
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@ -4,7 +4,7 @@ import Chisel._
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import Constants._
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import Constants._
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class TransactionInit extends Bundle {
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class TransactionInit extends Bundle {
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val ttype = Bits(width = 2)
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val ttype = Bits(width = TTYPE_BITS)
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val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
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val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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val address = Bits(width = PADDR_BITS)
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val data = Bits(width = MEM_DATA_BITS)
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val data = Bits(width = MEM_DATA_BITS)
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@ -15,20 +15,20 @@ class TransactionAbort extends Bundle {
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}
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}
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class ProbeRequest extends Bundle {
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class ProbeRequest extends Bundle {
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val ptype = Bits(width = 2)
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val ptype = Bits(width = PTYPE_BITS)
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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val address = Bits(width = PADDR_BITS)
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}
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}
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class ProbeReply extends Bundle {
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class ProbeReply extends Bundle {
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val ptype = Bits(width = 2)
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val ptype = Bits(width = PTYPE_BITS)
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val hasData = Bool()
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val hasData = Bool()
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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val data = Bits(width = MEM_DATA_BITS)
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val data = Bits(width = MEM_DATA_BITS)
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}
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}
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class TransactionReply extends Bundle {
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class TransactionReply extends Bundle {
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val ttype = Bits(width = 2)
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val ttype = Bits(width = TTYPE_BITS)
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val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
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val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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val data = Bits(width = MEM_DATA_BITS)
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val data = Bits(width = MEM_DATA_BITS)
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