Support eccBytes > 1
This commit is contained in:
Andrew Waterman
parent
8e4be40efc
commit
b9a934ae28
@ -13,11 +13,12 @@ import util._
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import TLMessages._
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class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
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val eccBytes = cacheParams.dataECCBytes
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val addr = Bits(width = untagBits)
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val write = Bool()
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val wdata = UInt(width = cacheParams.dataECC.width(cacheParams.dataECCBytes*8) * rowBytes/cacheParams.dataECCBytes)
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val wdata = UInt(width = cacheParams.dataECC.width(eccBytes*8) * rowBytes/eccBytes)
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val wordMask = UInt(width = rowBytes / wordBytes)
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val byteMask = UInt(width = wordBytes)
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val eccMask = UInt(width = wordBytes / eccBytes)
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val way_en = Bits(width = nWays)
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}
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@ -31,7 +32,7 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val eccBits = cacheParams.dataECCBytes * 8
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val encBits = cacheParams.dataECC.width(eccBits)
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val encWordBits = encBits * (wordBits / eccBits)
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val eccMask = if (eccBits == wordBits) Seq(true.B) else (0 until wordBytes by eccBits/8).map(io.req.bits.byteMask(_))
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val eccMask = if (eccBits == wordBits) Seq(true.B) else io.req.bits.eccMask.toBools
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val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i)))
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val wWords = io.req.bits.wdata.grouped(encBits * (wordBits / eccBits))
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val addr = io.req.bits.addr >> rowOffBits
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@ -59,7 +60,9 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val eccBytes = cacheParams.dataECCBytes
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val eccBits = eccBytes * 8
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require(tECC.isInstanceOf[IdentityCode])
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require(eccBytes == 1)
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require(isPow2(eccBytes) && eccBytes <= wordBytes)
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require(eccBytes == 1 || !dECC.isInstanceOf[IdentityCode])
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val usingRMW = eccBytes > 1 || usingAtomics
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// tags
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val replacer = cacheParams.replacement
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@ -93,7 +96,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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s1_req := io.cpu.req.bits
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s1_req.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaReadArb.io.out.bits.idx, io.cpu.req.bits.addr(blockOffBits-1,0))
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}
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val s1_read = isRead(s1_req.cmd)
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val s1_read = needsRead(s1_req)
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val s1_write = isWrite(s1_req.cmd)
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val s1_readwrite = s1_read || s1_write
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val s1_sfence = s1_req.cmd === M_SFENCE
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@ -114,12 +117,13 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val uncachedReqs = Seq.fill(maxUncachedInFlight) { Reg(new HellaCacheReq) }
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// hit initiation path
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dataArb.io.in(3).valid := io.cpu.req.valid && isRead(io.cpu.req.bits.cmd)
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val s0_read = needsRead(io.cpu.req.bits)
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dataArb.io.in(3).valid := io.cpu.req.valid && s0_read
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dataArb.io.in(3).bits.write := false
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dataArb.io.in(3).bits.addr := io.cpu.req.bits.addr
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dataArb.io.in(3).bits.wordMask := UIntToOH(io.cpu.req.bits.addr.extract(rowOffBits-1,offsetlsb))
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dataArb.io.in(3).bits.way_en := ~UInt(0, nWays)
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when (!dataArb.io.in(3).ready && isRead(io.cpu.req.bits.cmd)) { io.cpu.req.ready := false }
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when (!dataArb.io.in(3).ready && s0_read) { io.cpu.req.ready := false }
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metaReadArb.io.in(2).valid := io.cpu.req.valid
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metaReadArb.io.in(2).bits.idx := io.cpu.req.bits.addr(idxMSB, idxLSB)
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metaReadArb.io.in(2).bits.way_en := ~UInt(0, nWays)
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@ -193,7 +197,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd)
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val s2_data_decoded = decodeData(s2_data)
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val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes))
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val s2_data_error = s2_read && (s2_data_decoded.map(_.error).grouped(wordBits/eccBits).map(_.reduce(_||_)).toSeq)(s2_word_idx)
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val s2_data_error = needsRead(s2_req) && (s2_data_decoded.map(_.error).grouped(wordBits/eccBits).map(_.reduce(_||_)).toSeq)(s2_word_idx)
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val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt
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val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt
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val s2_valid_hit_pre_data_ecc = s2_valid_masked && s2_readwrite && s2_hit
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@ -246,16 +250,16 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val pstore1_way = RegEnable(s1_hit_way, s1_valid_not_nacked && s1_write)
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val pstore1_mask = RegEnable(s1_mask, s1_valid_not_nacked && s1_write)
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val pstore1_storegen_data = Wire(init = pstore1_data)
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val pstore1_amo = Bool(usingAtomics) && isRead(pstore1_cmd)
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val pstore1_rmw = Bool(usingRMW) && RegEnable(s1_read, s1_valid_not_nacked && s1_write)
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val pstore1_valid = Wire(Bool())
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val pstore2_valid = Reg(Bool())
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any_pstore_valid := pstore1_valid || pstore2_valid
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val pstore_drain_structural = pstore1_valid && pstore2_valid && ((s1_valid && s1_write) || pstore1_amo)
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val pstore_drain_opportunistic = !(io.cpu.req.valid && isRead(io.cpu.req.bits.cmd))
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val pstore_drain_structural = pstore1_valid && pstore2_valid && ((s1_valid && s1_write) || pstore1_rmw)
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val pstore_drain_opportunistic = !(io.cpu.req.valid && s0_read)
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val pstore_drain_on_miss = releaseInFlight || io.cpu.s2_nack
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val pstore_drain =
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Bool(usingAtomics) && pstore_drain_structural ||
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(((pstore1_valid && !pstore1_amo) || pstore2_valid) && (pstore_drain_opportunistic || pstore_drain_on_miss))
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Bool(usingRMW) && pstore_drain_structural ||
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(((pstore1_valid && !pstore1_rmw) || pstore2_valid) && (pstore_drain_opportunistic || pstore_drain_on_miss))
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pstore1_valid := {
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val s2_store_valid = s2_valid_hit && s2_write && !s2_sc_fail
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val pstore1_held = Reg(Bool())
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@ -275,13 +279,15 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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dataArb.io.in(0).bits.way_en := Mux(pstore2_valid, pstore2_way, pstore1_way)
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dataArb.io.in(0).bits.wdata := Fill(rowWords, Mux(pstore2_valid, pstore2_storegen_data, pstore1_data))
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dataArb.io.in(0).bits.wordMask := UIntToOH(Mux(pstore2_valid, pstore2_addr, pstore1_addr).extract(rowOffBits-1,offsetlsb))
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dataArb.io.in(0).bits.byteMask := Mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask)
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dataArb.io.in(0).bits.eccMask := eccMask(Mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask))
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// store->load RAW hazard detection
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val s1_idx = s1_req.addr(idxMSB, wordOffBits)
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def s1Depends(addr: UInt, mask: UInt) =
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addr(idxMSB, wordOffBits) === s1_req.addr(idxMSB, wordOffBits) &&
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Mux(s1_write, (eccByteMask(mask) & eccByteMask(s1_mask)).orR, (mask & s1_mask).orR)
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val s1_raw_hazard = s1_read &&
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((pstore1_valid && pstore1_addr(idxMSB, wordOffBits) === s1_idx && (pstore1_mask & s1_mask).orR) ||
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(pstore2_valid && pstore2_addr(idxMSB, wordOffBits) === s1_idx && (pstore2_storegen_mask & s1_mask).orR))
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((pstore1_valid && s1Depends(pstore1_addr, pstore1_mask)) ||
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(pstore2_valid && s1Depends(pstore2_addr, pstore2_storegen_mask)))
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when (s1_valid && s1_raw_hazard) { s1_nack := true }
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metaWriteArb.io.in(0).valid := (s2_valid_hit && s2_update_meta) || (s2_victimize && !s2_victim_dirty)
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@ -316,13 +322,13 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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M_XA_MAXU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAXU)._2))
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} else {
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// If no managers support atomics, assert fail if processor asks for them
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assert (!(tl_out_a.valid && pstore1_amo && s2_write && s2_uncached))
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assert (!(tl_out_a.valid && s2_read && s2_write && s2_uncached))
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Wire(new TLBundleA(edge.bundle))
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}
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tl_out_a.valid := (s2_valid_cached_miss && !s2_victim_dirty) ||
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(s2_valid_uncached && !uncachedInFlight.asUInt.andR)
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tl_out_a.bits := Mux(!s2_uncached, acquire, Mux(!s2_write, get, Mux(!pstore1_amo, put, atomics)))
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tl_out_a.bits := Mux(!s2_uncached, acquire, Mux(!s2_write, get, Mux(!s2_read, put, atomics)))
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// Set pending bits for outstanding TileLink transaction
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val a_sel = UIntToOH(a_source, maxUncachedInFlight+mmioOffset) >> mmioOffset
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@ -392,7 +398,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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dataArb.io.in(1).bits.way_en := s2_victim_way
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dataArb.io.in(1).bits.wdata := tl_out.d.bits.data
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dataArb.io.in(1).bits.wordMask := ~UInt(0, rowBytes / wordBytes)
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dataArb.io.in(1).bits.byteMask := ~UInt(0, wordBytes)
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dataArb.io.in(1).bits.eccMask := ~UInt(0, wordBytes / eccBytes)
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// tag updates on refill
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metaWriteArb.io.in(1).valid := grantIsCached && d_done
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assert(!metaWriteArb.io.in(1).valid || metaWriteArb.io.in(1).ready)
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@ -538,10 +544,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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io.cpu.resp.bits.store_data := pstore1_data
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// AMOs
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if (usingAtomics) {
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if (usingRMW) {
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val amoalu = Module(new AMOALU(xLen))
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amoalu.io.mask := pstore1_mask
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amoalu.io.cmd := pstore1_cmd
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amoalu.io.cmd := (if (usingAtomics) pstore1_cmd else M_XWR)
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amoalu.io.lhs := s2_data_word
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amoalu.io.rhs := pstore1_data
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pstore1_storegen_data := amoalu.io.out
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@ -585,4 +591,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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def encodeData(x: UInt) = x.grouped(eccBits).map(dECC.encode(_)).asUInt
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def dummyEncodeData(x: UInt) = x.grouped(eccBits).map(dECC.swizzle(_)).asUInt
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def decodeData(x: UInt) = x.grouped(dECC.width(eccBits)).map(dECC.decode(_))
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def eccMask(byteMask: UInt) = byteMask.grouped(eccBytes).map(_.orR).asUInt
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def eccByteMask(byteMask: UInt) = FillInterleaved(eccBytes, eccMask(byteMask))
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def needsRead(req: HellaCacheReq) =
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isRead(req.cmd) ||
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(isWrite(req.cmd) && (req.cmd === M_PWR || mtSize(req.typ) < log2Ceil(eccBytes)))
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}
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