added s_wait_puts to L2AcquireTracker
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@ -591,7 +591,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int) extends L2XactTrack
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class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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val io = new L2XactTrackerIO
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val io = new L2XactTrackerIO
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val s_idle :: s_meta_read :: s_meta_resp :: s_wb_req :: s_wb_resp :: s_probe :: s_outer_acquire :: s_outer_grant :: s_outer_finish :: s_data_read :: s_data_resp :: s_data_write :: s_inner_grant :: s_meta_write :: s_inner_finish :: Nil = Enum(UInt(), 15)
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val s_idle :: s_meta_read :: s_meta_resp :: s_wb_req :: s_wb_resp :: s_probe :: s_outer_acquire :: s_outer_grant :: s_outer_finish :: s_data_read :: s_data_resp :: s_wait_puts :: s_data_write :: s_inner_grant :: s_meta_write :: s_inner_finish :: Nil = Enum(UInt(), 16)
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val state = Reg(init=s_idle)
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val state = Reg(init=s_idle)
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val xact_src = Reg(io.inner.acquire.bits.header.src.clone)
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val xact_src = Reg(io.inner.acquire.bits.header.src.clone)
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@ -602,12 +602,15 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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val xact_meta = Reg{ new L2Metadata }
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val xact_meta = Reg{ new L2Metadata }
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val xact_way_en = Reg{ Bits(width = nWays) }
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val xact_way_en = Reg{ Bits(width = nWays) }
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val pending_coh = Reg{ xact_meta.coh.clone }
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val pending_coh = Reg{ xact_meta.coh.clone }
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val pending_puts = Reg(init=Bits(0, width = innerDataBeats))
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pending_puts := (pending_puts | addPendingBit(io.inner.acquire))
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val is_hit = xact_tag_match && xact_meta.coh.outer.isHit(xact.op_code())
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val is_hit = xact_tag_match && xact_meta.coh.outer.isHit(xact.op_code())
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val do_allocate = xact.allocate()
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val do_allocate = xact.allocate()
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val needs_writeback = !xact_tag_match && do_allocate &&
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val needs_writeback = !xact_tag_match && do_allocate &&
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(xact_meta.coh.outer.requiresVoluntaryWriteback() ||
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(xact_meta.coh.outer.requiresVoluntaryWriteback() ||
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xact_meta.coh.inner.requiresProbesOnVoluntaryWriteback())
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xact_meta.coh.inner.requiresProbesOnVoluntaryWriteback())
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val needs_more_put_data = !pending_puts.andR
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val release_count = Reg(init = UInt(0, width = log2Up(nCoherentClients+1)))
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val release_count = Reg(init = UInt(0, width = log2Up(nCoherentClients+1)))
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val pending_probes = Reg(init = Bits(0, width = nCoherentClients))
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val pending_probes = Reg(init = Bits(0, width = nCoherentClients))
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@ -808,6 +811,9 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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xact := io.iacq()
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xact := io.iacq()
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xact.data := UInt(0)
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xact.data := UInt(0)
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wmask_buffer.foreach { w => w := UInt(0) }
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wmask_buffer.foreach { w => w := UInt(0) }
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pending_puts := Mux(io.iacq().isBuiltInType(Acquire.putBlockType),
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UInt(0),
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SInt(-1, width = innerDataBeats)).toUInt
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pending_reads := Mux(io.iacq().isSubBlockType(),
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pending_reads := Mux(io.iacq().isSubBlockType(),
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UIntToOH(io.iacq().addr_beat),
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UIntToOH(io.iacq().addr_beat),
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SInt(-1, width = innerDataBeats)).toUInt
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SInt(-1, width = innerDataBeats)).toUInt
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@ -876,7 +882,9 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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}
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}
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when(release_count === UInt(0)) {
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when(release_count === UInt(0)) {
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state := Mux(is_hit,
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state := Mux(is_hit,
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Mux(pending_writes.orR, s_data_write, s_data_read),
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Mux(pending_writes.orR,
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Mux(needs_more_put_data, s_wait_puts, s_data_write),
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s_data_read),
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s_outer_acquire)
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s_outer_acquire)
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}
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}
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}
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}
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@ -901,7 +909,9 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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state := s_outer_finish
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state := s_outer_finish
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}.otherwise {
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}.otherwise {
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state := Mux(!do_allocate, s_inner_grant,
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state := Mux(!do_allocate, s_inner_grant,
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Mux(pending_writes.orR, s_data_write, s_data_read))
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Mux(pending_writes.orR,
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Mux(needs_more_put_data, s_wait_puts, s_data_write),
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s_data_read))
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}
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}
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}
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}
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}
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}
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@ -910,7 +920,9 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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io.outer.finish.valid := Bool(true)
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io.outer.finish.valid := Bool(true)
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when(io.outer.finish.ready) {
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when(io.outer.finish.ready) {
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state := Mux(!do_allocate, s_inner_grant,
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state := Mux(!do_allocate, s_inner_grant,
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Mux(pending_writes.orR, s_data_write, s_data_read))
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Mux(pending_writes.orR,
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Mux(needs_more_put_data, s_wait_puts, s_data_write),
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s_data_read))
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}
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}
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}
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}
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is(s_data_read) {
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is(s_data_read) {
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@ -927,12 +939,15 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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mergeDataInternal(io.data.resp.bits.addr_beat, io.data.resp.bits.data)
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mergeDataInternal(io.data.resp.bits.addr_beat, io.data.resp.bits.data)
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pending_resps := pending_resps & ~UIntToOH(io.data.resp.bits.addr_beat)
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pending_resps := pending_resps & ~UIntToOH(io.data.resp.bits.addr_beat)
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when(PopCount(pending_resps) <= UInt(1)) {
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when(PopCount(pending_resps) <= UInt(1)) {
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state := Mux(pending_writes.orR, s_data_write, s_inner_grant)
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state := Mux(pending_writes.orR,
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Mux(needs_more_put_data, s_wait_puts, s_data_write),
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s_inner_grant)
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}
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}
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}
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}
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}
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}
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is(s_wait_puts) { when(!needs_more_put_data) { state := s_data_write } }
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is(s_data_write) {
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is(s_data_write) {
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io.data.write.valid := pending_writes.orR //TODO make sure all acquire data is present
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io.data.write.valid := pending_writes.orR
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when(io.data.write.ready) {
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when(io.data.write.ready) {
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when(PopCount(pending_writes) <= UInt(1)) { state := s_inner_grant }
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when(PopCount(pending_writes) <= UInt(1)) { state := s_inner_grant }
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}
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}
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