riscv/rocket-chip
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refactor IPIs; use new tohost/fromhost protocol

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This commit is contained in:
Andrew Waterman 2012-08-03 19:00:34 -07:00
parent 6510f020c7
commit b94e6915ab
3 changed files with 37 additions and 29 deletions
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21
rocket/src/main/scala/dpath_util.scala
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@ -122,13 +122,13 @@ class rocketDpathPCR extends Component
val rdata = Bits();
val raddr = Mux(io.r.en, io.r.addr, io.host.pcr_req.bits.addr(4,0))
io.host.pcr_rep.valid := io.host.pcr_req.valid && !io.r.en && !io.host.pcr_req.bits.rw
io.host.pcr_rep.valid := io.host.pcr_req.fire()
io.host.pcr_rep.bits := rdata
val wen = io.w.en || io.host.pcr_req.valid && io.host.pcr_req.bits.rw
val wen = io.w.en || !io.r.en && io.host.pcr_req.valid && io.host.pcr_req.bits.rw
val waddr = Mux(io.w.en, io.w.addr, io.host.pcr_req.bits.addr)
val wdata = Mux(io.w.en, io.w.data, io.host.pcr_req.bits.data)
io.host.pcr_req.ready := Mux(io.host.pcr_req.bits.rw, !io.w.en, !io.r.en)
io.host.pcr_req.ready := !io.w.en && !io.r.en
io.ptbr_wen := reg_status_vm.toBool && wen && (waddr === PCR_PTBR);
io.status := Cat(reg_status_im, Bits(0,7), reg_status_vm, reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, reg_status_ec, reg_status_ev, reg_status_ef, reg_status_et);
@ -176,9 +176,11 @@ class rocketDpathPCR extends Component
io.irq_timer := r_irq_timer;
io.irq_ipi := r_irq_ipi;
io.host.ipi.valid := io.w.en && io.w.addr === PCR_SEND_IPI
io.host.ipi.bits := io.w.data
io.replay := io.host.ipi.valid && !io.host.ipi.ready
io.host.ipi_req.valid := io.w.en && io.w.addr === PCR_SEND_IPI
io.host.ipi_req.bits := io.w.data
io.replay := io.host.ipi_req.valid && !io.host.ipi_req.ready
when (io.host.pcr_req.fire() && !io.host.pcr_req.bits.rw && io.host.pcr_req.bits.addr === PCR_TOHOST) { reg_tohost := UFix(0) }
when (wen) {
when (waddr === PCR_STATUS) {
@ -198,8 +200,8 @@ class rocketDpathPCR extends Component
when (waddr === PCR_COUNT) { reg_count := wdata(31,0).toUFix; }
when (waddr === PCR_COMPARE) { reg_compare := wdata(31,0).toUFix; r_irq_timer := Bool(false); }
when (waddr === PCR_COREID) { reg_coreid := wdata(15,0) }
when (waddr === PCR_FROMHOST) { reg_fromhost := wdata; reg_tohost := Bits(0) }
when (waddr === PCR_TOHOST) { reg_tohost := wdata; reg_fromhost := Bits(0) }
when (waddr === PCR_FROMHOST) { when (reg_fromhost === UFix(0) || io.w.en) { reg_fromhost := wdata } }
when (waddr === PCR_TOHOST) { when (reg_tohost === UFix(0)) { reg_tohost := wdata } }
when (waddr === PCR_CLR_IPI) { r_irq_ipi := wdata(0) }
when (waddr === PCR_K0) { reg_k0 := wdata; }
when (waddr === PCR_K1) { reg_k1 := wdata; }
@ -207,6 +209,9 @@ class rocketDpathPCR extends Component
when (waddr === PCR_VECBANK) { reg_vecbank:= wdata(7,0) }
}
io.host.ipi_rep.ready := Bool(true)
when (io.host.ipi_rep.valid) { r_irq_ipi := Bool(true) }
rdata := io.status // raddr === PCR_STATUS
switch (raddr) {
is (PCR_EPC) { rdata := Cat(Fill(64-VADDR_BITS-1, reg_epc(VADDR_BITS)), reg_epc); }

42
rocket/src/main/scala/htif.scala
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@ -28,7 +28,8 @@ class ioHTIF extends Bundle
val debug = new ioDebug
val pcr_req = (new FIFOIO) { new PCRReq }.flip
val pcr_rep = (new FIFOIO) { Bits(width = 64) }
val ipi = (new FIFOIO) { Bits(width = log2Up(NTILES)) }
val ipi_req = (new FIFOIO) { Bits(width = log2Up(NTILES)) }
val ipi_rep = (new FIFOIO) { Bool() }.flip
}
class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends Component
@ -93,7 +94,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
}
val rx_done = rx_word_done && Mux(rx_word_count === UFix(0), next_cmd != cmd_writemem && next_cmd != cmd_writecr, rx_word_count === size || rx_word_count(log2Up(packet_ram_depth)-1,0) === UFix(0))
val tx_size = Mux(!nack && (cmd === cmd_readmem || cmd === cmd_readcr), size, UFix(0))
val tx_size = Mux(!nack && (cmd === cmd_readmem || cmd === cmd_readcr || cmd === cmd_writecr), size, UFix(0))
val tx_done = io.host.out.ready && tx_subword_count.andR && (tx_word_count === tx_size || tx_word_count > UFix(0) && packet_ram_raddr.andR)
val mem_acked = Reg(resetVal = Bool(false))
@ -195,31 +196,32 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
val cpu = io.cpu(i)
val me = pcr_coreid === UFix(i)
cpu.pcr_req.valid := my_ipi || state === state_pcr_req && me
cpu.pcr_req.bits.rw := my_ipi || cmd === cmd_writecr
cpu.pcr_req.bits.addr := Mux(my_ipi, PCR_CLR_IPI, pcr_addr)
cpu.pcr_req.bits.data := my_ipi | pcr_wdata
cpu.pcr_req.valid := state === state_pcr_req && me && pcr_addr != PCR_RESET
cpu.pcr_req.bits.rw := cmd === cmd_writecr
cpu.pcr_req.bits.addr := pcr_addr
cpu.pcr_req.bits.data := pcr_wdata
cpu.reset := my_reset
when (cpu.ipi_rep.ready) {
my_ipi := Bool(false)
}
cpu.ipi_rep.valid := my_ipi
cpu.ipi_req.ready := Bool(true)
for (j <- 0 until ncores) {
when (io.cpu(j).ipi.valid && io.cpu(j).ipi.bits === UFix(i)) {
when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UFix(i)) {
my_ipi := Bool(true)
}
}
cpu.ipi.ready := Bool(true)
when (my_ipi) {
my_ipi := !cpu.pcr_req.ready
}
when (state === state_pcr_req && me && !my_ipi && cpu.pcr_req.ready) {
when (cmd === cmd_writecr) {
state := state_tx
when (pcr_addr === PCR_RESET) {
my_reset := pcr_wdata(0)
}
}.otherwise {
when (cpu.pcr_req.valid && cpu.pcr_req.ready) {
state := state_pcr_resp
}
when (state === state_pcr_req && me && pcr_addr === PCR_RESET) {
when (cmd === cmd_writecr) {
my_reset := pcr_wdata(0)
}
rdata := my_reset.toBits
state := state_tx
}
cpu.pcr_rep.ready := Bool(true)
@ -229,14 +231,14 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
}
pcr_mux.io.sel(i) := me
pcr_mux.io.in(i) := Mux(pcr_addr === PCR_RESET, Cat(Bits(0, 63), my_reset), rdata)
pcr_mux.io.in(i) := rdata
}
val tx_cmd = Mux(nack, cmd_nack, cmd_ack)
val tx_cmd_ext = Cat(Bits(0, 4-tx_cmd.getWidth), tx_cmd)
val tx_header = Cat(addr, seqno, tx_size, tx_cmd_ext)
val tx_data = Mux(tx_word_count === UFix(0), tx_header,
Mux(cmd === cmd_readcr, pcr_mux.io.out,
Mux(cmd === cmd_readcr || cmd === cmd_writecr, pcr_mux.io.out,
packet_ram(packet_ram_raddr)))
io.host.in.ready := state === state_rx

3
rocket/src/main/scala/top.scala
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@ -40,7 +40,8 @@ class Top extends Component
tile.io.host.reset := Reg(Reg(hl.reset))
tile.io.host.pcr_req <> Queue(hl.pcr_req)
hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
hl.ipi <> Queue(tile.io.host.ipi)
hl.ipi_req <> Queue(tile.io.host.ipi_req)
tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
error_mode = error_mode || Reg(tile.io.host.debug.error_mode)
tl.xact_init <> Queue(tile.io.tilelink.xact_init)