you can 'hit' with putblocks even when the tag doesn't match but you still better writeback
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@ -859,7 +859,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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val _tag_match = io.meta.resp.bits.tag_match
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val _tag_match = io.meta.resp.bits.tag_match
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val _is_hit = (if(isLastLevelCache)
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val _is_hit = (if(isLastLevelCache)
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(xact.isBuiltInType(Acquire.putBlockType) ||
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(xact.isBuiltInType(Acquire.putBlockType) ||
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_coh.outer.isValid())
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_tag_match && _coh.outer.isValid())
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else (_tag_match && _coh.outer.isHit(xact.op_code())))
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else (_tag_match && _coh.outer.isHit(xact.op_code())))
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val _needs_writeback = !_tag_match && do_allocate &&
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val _needs_writeback = !_tag_match && do_allocate &&
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@ -871,17 +871,23 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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pending_probes := mask_incoherent
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pending_probes := mask_incoherent
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release_count := PopCount(mask_incoherent)
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release_count := PopCount(mask_incoherent)
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}
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}
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state := Mux(!_tag_match,
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state := Mux(_needs_writeback, s_wb_req,
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Mux(_needs_writeback, s_wb_req, s_outer_acquire),
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Mux(_needs_inner_probes, s_inner_probe,
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Mux(_needs_inner_probes, s_inner_probe,
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Mux(!is_hit, s_outer_acquire,
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Mux(!_is_hit, s_outer_acquire,
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Mux(pending_reads.orR, s_data_read,
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Mux(pending_reads.orR, s_data_read,
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Mux(!pending_writes.orR, s_inner_grant,
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Mux(!pending_writes.orR, s_inner_grant,
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Mux(needs_more_put_data, s_wait_puts, s_data_write))))))
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Mux(needs_more_put_data, s_wait_puts, s_data_write))))))
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}
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}
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}
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}
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is(s_wb_req) { when(io.wb.req.ready) { state := s_wb_resp } }
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is(s_wb_req) { when(io.wb.req.ready) { state := s_wb_resp } }
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is(s_wb_resp) { when(io.wb.resp.valid) { state := s_outer_acquire } }
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is(s_wb_resp) {
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when(io.wb.resp.valid) {
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state := Mux(!is_hit, s_outer_acquire,
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Mux(pending_reads.orR, s_data_read,
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Mux(!pending_writes.orR, s_inner_grant,
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Mux(needs_more_put_data, s_wait_puts, s_data_write))))
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}
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}
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is(s_inner_probe) {
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is(s_inner_probe) {
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// Send probes
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// Send probes
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when(io.inner.probe.ready) {
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when(io.inner.probe.ready) {
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