riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Simplify frontend virtual address extension code

Browse Source
This commit is contained in:
Andrew Waterman 2016-07-14 12:05:09 -07:00
parent 1699622730
commit b8884e8143
1 changed files with 1 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
rocket/src/main/scala/frontend.scala
View File

@ -53,10 +53,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
val s2_resp_valid = Wire(Bool()) val s2_resp_valid = Wire(Bool())
val s2_resp_data = Wire(UInt(width = rowBits)) val s2_resp_data = Wire(UInt(width = rowBits))
val ntpc_0 = ~(~s1_pc | (coreInstBytes*fetchWidth-1)) + UInt(coreInstBytes*fetchWidth) val ntpc = ~(~s1_pc | (coreInstBytes*fetchWidth-1)) + UInt(coreInstBytes*fetchWidth)
val ntpc = // don't increment PC into virtual address space hole
if (vaddrBitsExtended == vaddrBits) ntpc_0
else Cat(s1_pc(vaddrBits-1) & ntpc_0(vaddrBits-1), ntpc_0)
val predicted_npc = Wire(init = ntpc) val predicted_npc = Wire(init = ntpc)
val icmiss = s2_valid && !s2_resp_valid val icmiss = s2_valid && !s2_resp_valid
val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt