From d5c9eb0f54e7e27f0d07126c79dbc6c1e701a6c5 Mon Sep 17 00:00:00 2001 From: Huy Vo Date: Mon, 12 Aug 2013 20:52:18 -0700 Subject: [PATCH] reset -> resetVal, getReset -> reset --- uncore/src/llc.scala | 2 +- uncore/src/slowio.scala | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/uncore/src/llc.scala b/uncore/src/llc.scala index 3e7c2cd5..db49f027 100644 --- a/uncore/src/llc.scala +++ b/uncore/src/llc.scala @@ -370,7 +370,7 @@ class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, tagLeaf: Mem[UInt], da val s3_rdy = Bool() val replay_s2_rdy = Bool() - val s1_valid = Reg(update = io.cpu.req_cmd.fire() || replay_s2 && replay_s2_rdy, reset = Bool(false)) + val s1_valid = Reg(update = io.cpu.req_cmd.fire() || replay_s2 && replay_s2_rdy, resetVal = Bool(false)) val s1 = Reg(new MemReqCmd) when (io.cpu.req_cmd.fire()) { s1 := io.cpu.req_cmd.bits } when (replay_s2 && replay_s2_rdy) { s1 := s2 } diff --git a/uncore/src/slowio.scala b/uncore/src/slowio.scala index 4d42fccf..b8be1ed7 100644 --- a/uncore/src/slowio.scala +++ b/uncore/src/slowio.scala @@ -47,7 +47,7 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module val out_slow_bits = Reg(data) val fromhost_q = Module(new Queue(data,1)) - fromhost_q.io.enq.valid := rising && (io.in_slow.valid && in_slow_rdy || this.getReset) + fromhost_q.io.enq.valid := rising && (io.in_slow.valid && in_slow_rdy || this.reset) fromhost_q.io.enq.bits := io.in_slow.bits fromhost_q.io.deq <> io.in_fast @@ -58,7 +58,7 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module when (held) { in_slow_rdy := fromhost_q.io.enq.ready out_slow_val := tohost_q.io.deq.valid - out_slow_bits := Mux(this.getReset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits) + out_slow_bits := Mux(this.reset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits) } io.in_slow.ready := in_slow_rdy