riscv/rocket-chip
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flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs

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Rimas Avizienis
2011-11-14 04:13:13 -08:00
parent 890bfa7c48
commit b791010bb1
6 changed files with 128 additions and 105 deletions
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2
rocket/src/main/scala/dpath_util.scala
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@ -53,6 +53,7 @@ class ioDpathPCR extends Bundle()
val pc = UFix(VADDR_BITS, 'input);
val badvaddr = UFix(VADDR_BITS, 'input);
val eret = Bool('input);
val ptbr_wen = Bool('output);
val irq_timer = Bool('output);
val irq_ipi = Bool('output);
}
@ -90,6 +91,7 @@ class rocketDpathPCR extends Component
val reg_status = Cat(reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, Bits(0,1), reg_status_ev, reg_status_ef, reg_status_et);
val rdata = Wire() { Bits() };
io.ptbr_wen := reg_status_vm.toBool && !io.exception && io.w.en && (io.w.addr === PCR_PTBR);
io.status := Cat(reg_status_vm, reg_status_im, reg_status);
io.evec := reg_ebase;
io.ptbr := reg_ptbr;