riscv/rocket-chip
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flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs

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Rimas Avizienis
2011-11-14 04:13:13 -08:00
parent 890bfa7c48
commit b791010bb1
6 changed files with 128 additions and 105 deletions
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4
rocket/src/main/scala/consts.scala
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@ -138,6 +138,10 @@ object Constants
val M_XA_MAX = Bits("b1101", 4);
val M_XA_MINU = Bits("b1110", 4);
val M_XA_MAXU = Bits("b1111", 4);
val SYNC_N = Bits(0,2);
val SYNC_D = Bits(1,2);
val SYNC_I = Bits(2,2);
val PCR_STATUS = UFix( 0, 5);
val PCR_EPC = UFix( 1, 5);