make unit tests local to the packages being tested

groundtest/src/main/scala/CacheFillTest.scala

@@ -4,7 +4,6 @@ import Chisel._
 import uncore.tilelink._
 import uncore.constants._
 import uncore.agents._
-import groundtest.common._
 import cde.{Parameters, Field}
 
 class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)

groundtest/src/main/scala/Comparator.scala

@@ -5,7 +5,6 @@ import uncore.tilelink._
 import uncore.constants._
 import junctions._
 import rocket._
-import groundtest.common._
 import scala.util.Random
 import cde.{Parameters, Field}
 

groundtest/src/main/scala/Generator.scala

@@ -6,7 +6,6 @@ import uncore.devices.NTiles
 import uncore.constants._
 import junctions._
 import rocket._
-import groundtest.common._
 import scala.util.Random
 import cde.{Parameters, Field}
 

groundtest/src/main/scala/NastiTest.scala

@@ -4,7 +4,6 @@ import Chisel._
 import uncore.tilelink._
 import uncore.converters._
 import junctions._
-import groundtest.common._
 import cde.Parameters
 
 class NastiGenerator(id: Int)(implicit val p: Parameters) extends Module

groundtest/src/main/scala/Regression.scala

@@ -4,9 +4,8 @@ import Chisel._
 import uncore.tilelink._
 import uncore.constants._
 import uncore.agents._
-import junctions.{ParameterizedBundle, HasAddrMapParameters}
+import junctions.{ParameterizedBundle, HasAddrMapParameters, Timer}
 import rocket.HellaCacheIO
-import groundtest.common._
 import cde.{Parameters, Field}
 
 class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p) {

groundtest/src/main/scala/Tile.scala

@@ -1,4 +1,4 @@
-package groundtest.common
+package groundtest
 
 import Chisel._
 import rocket._

groundtest/src/main/scala/TraceGen.scala

@@ -22,7 +22,6 @@ import uncore.constants._
 import uncore.devices.NTiles
 import junctions._
 import rocket._
-import groundtest.common._
 import scala.util.Random
 import cde.{Parameters, Field}
 

groundtest/src/main/scala/Util.scala

@@ -1,56 +1,7 @@
-package groundtest.common
+package groundtest
 
 import Chisel._
 
-// ============
-// Static timer
-// ============
-
-// Timer with a statically-specified period.
-// Can take multiple inflight start-stop events with ID
-// Will continue to count down as long as at least one event is inflight
-
-class Timer(initCount: Int, maxInflight: Int) extends Module {
-  val io = new Bundle {
-    val start = Valid(UInt(width = log2Up(maxInflight))).flip
-    val stop = Valid(UInt(width = log2Up(maxInflight))).flip
-    val timeout = Valid(UInt(width = log2Up(maxInflight)))
-  }
-
-  val inflight = Reg(init = Vec.fill(maxInflight) { Bool(false) })
-  val countdown = Reg(UInt(width = log2Up(initCount)))
-  val active = inflight.reduce(_ || _)
-
-  when (active) {
-    countdown := countdown - UInt(1)
-  }
-
-  when (io.start.valid) {
-    inflight(io.start.bits) := Bool(true)
-    countdown := UInt(initCount - 1)
-  }
-  when (io.stop.valid) {
-    inflight(io.stop.bits) := Bool(false)
-  }
-
-  io.timeout.valid := countdown === UInt(0) && active
-  io.timeout.bits := PriorityEncoder(inflight)
-
-  assert(!io.stop.valid || inflight(io.stop.bits),
-         "Timer stop for transaction that's not inflight")
-}
-
-object Timer {
-  def apply(initCount: Int, start: Bool, stop: Bool): Bool = {
-    val timer = Module(new Timer(initCount, 1))
-    timer.io.start.valid := start
-    timer.io.start.bits  := UInt(0)
-    timer.io.stop.valid  := stop
-    timer.io.stop.bits   := UInt(0)
-    timer.io.timeout.valid
-  }
-}
-
 // =============
 // Dynamic timer
 // =============

junctions/src/main/scala/unittests/MiscNastiTests.scala

@@ -1,9 +1,8 @@
-package groundtest.unittests
+package junctions.unittests
 
 import Chisel._
 import junctions._
 import junctions.NastiConstants._
-import groundtest.common._
 import cde.Parameters
 
 class NastiDriver(dataWidth: Int, burstLen: Int, nBursts: Int)
@@ -76,12 +75,6 @@ class NastiDriver(dataWidth: Int, burstLen: Int, nBursts: Int)
 
   assert(!io.nasti.r.valid || read_data === expected_data,
     s"NastiDriver got wrong data")
-
-  val ar_timeout = Timer(1024, io.nasti.ar.fire(), io.nasti.r.fire())
-  val aw_timeout = Timer(1024, io.nasti.aw.fire(), io.nasti.b.fire())
-
-  assert(!ar_timeout && !aw_timeout,
-    s"NastiDriver for $name timed out")
 }
 
 

junctions/src/main/scala/unittests/MultiWidthFifoTest.scala

@@ -1,4 +1,4 @@
-package groundtest.unittests
+package junctions.unittests
 
 import Chisel._
 import junctions._

junctions/src/main/scala/unittests/NastiDemuxTest.scala

@@ -1,4 +1,4 @@
-package groundtest.unittests
+package junctions.unittests
 
 import Chisel._
 import junctions._

junctions/src/main/scala/unittests/UnitTest.scala

@@ -1,13 +1,7 @@
-package groundtest.unittests
+package junctions.unittests
 
 import Chisel._
 import junctions._
-import junctions.NastiConstants._
-import uncore.tilelink._
-import uncore.converters._
-import uncore.constants._
-import uncore.devices._
-import groundtest.common._
 import cde.{Field, Parameters}
 
 abstract class UnitTest extends Module {
@@ -23,7 +17,11 @@ abstract class UnitTest extends Module {
 
 case object UnitTests extends Field[Parameters => Seq[UnitTest]]
 
-class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {
+class UnitTestSuite(implicit p: Parameters) extends Module {
+  val io = new Bundle {
+    val finished = Bool(OUTPUT)
+  }
+
   val tests = p(UnitTests)(p)
 
   val s_idle :: s_start :: s_wait :: s_done :: Nil = Enum(Bits(), 4)
@@ -39,17 +37,27 @@ class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {
     state := Mux(test_idx === UInt(tests.size - 1), s_done, s_start)
   }
 
-  io.status.timeout.valid := Bool(false)
+  val timer = Module(new Timer(1000, tests.size))
+
   tests.zipWithIndex.foreach { case (mod, i) =>
     mod.io.start := (state === s_start) && test_idx === UInt(i)
-    val timeout = Timer(1000, mod.io.start, mod.io.finished)
-    assert(!timeout, s"UnitTest ${mod.getClass.getSimpleName} timed out")
-    when (timeout) {
-      io.status.timeout.valid := Bool(true)
-      io.status.timeout.bits := UInt(i)
+    when (test_idx === UInt(i)) {
+      timer.io.start.valid := mod.io.start
+      timer.io.start.bits := UInt(i)
+      timer.io.stop.valid := mod.io.finished
+      timer.io.stop.bits := UInt(i)
     }
   }
-  io.status.finished := (state === s_done)
-  io.status.error.valid := Bool(false)
+  io.finished := (state === s_done)
 
+  assert(!timer.io.timeout.valid, "UnitTest timed out")
+}
+
+object JunctionsUnitTests {
+  def apply(implicit p: Parameters): Seq[UnitTest] =
+    Seq(
+      Module(new MultiWidthFifoTest),
+      Module(new AtosConverterTest),
+      Module(new NastiMemoryDemuxTest),
+      Module(new HastiTest))
 }

junctions/src/main/scala/util.scala

@@ -312,3 +312,54 @@ class MultiWidthFifo(inW: Int, outW: Int, n: Int) extends Module {
     io.in.ready := size < UInt(n * nBeats)
   }
 }
+
+// ============
+// Static timer
+// ============
+
+// Timer with a statically-specified period.
+// Can take multiple inflight start-stop events with ID
+// Will continue to count down as long as at least one event is inflight
+
+class Timer(initCount: Int, maxInflight: Int) extends Module {
+  val io = new Bundle {
+    val start = Valid(UInt(width = log2Up(maxInflight))).flip
+    val stop = Valid(UInt(width = log2Up(maxInflight))).flip
+    val timeout = Valid(UInt(width = log2Up(maxInflight)))
+  }
+
+  val inflight = Reg(init = Vec.fill(maxInflight) { Bool(false) })
+  val countdown = Reg(UInt(width = log2Up(initCount)))
+  val active = inflight.reduce(_ || _)
+
+  when (active) {
+    countdown := countdown - UInt(1)
+  }
+
+  when (io.start.valid) {
+    inflight(io.start.bits) := Bool(true)
+    countdown := UInt(initCount - 1)
+  }
+  when (io.stop.valid) {
+    inflight(io.stop.bits) := Bool(false)
+  }
+
+  io.timeout.valid := countdown === UInt(0) && active
+  io.timeout.bits := PriorityEncoder(inflight)
+
+  assert(!io.stop.valid || inflight(io.stop.bits),
+         "Timer stop for transaction that's not inflight")
+}
+
+object Timer {
+  def apply(initCount: Int, start: Bool, stop: Bool): Bool = {
+    val timer = Module(new Timer(initCount, 1))
+    timer.io.start.valid := start
+    timer.io.start.bits  := UInt(0)
+    timer.io.stop.valid  := stop
+    timer.io.stop.bits   := UInt(0)
+    timer.io.timeout.valid
+  }
+}
+
+

src/main/scala/DirectGroundTest.scala

@@ -3,7 +3,6 @@ package rocketchip
 import Chisel._
 import cde.{Parameters, Field}
 import groundtest._
-import groundtest.common._
 import uncore.tilelink._
 import uncore.agents._
 

src/main/scala/TestConfigs.scala

@@ -2,14 +2,14 @@ package rocketchip
 
 import Chisel._
 import groundtest._
-import groundtest.unittests._
-import groundtest.common._
 import rocket._
 import uncore.tilelink._
 import uncore.coherence._
 import uncore.agents._
 import uncore.devices.NTiles
+import uncore.unittests._
 import junctions._
+import junctions.unittests._
 import scala.collection.mutable.LinkedHashSet
 import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
 import scala.math.max
@@ -44,7 +44,7 @@ class WithGroundTest extends Config(
       (0 until site(NTiles)).map { i =>
         val tileSettings = site(GroundTestKey)(i)
         (r: Bool, p: Parameters) => {
-          Module(new GroundTestTile(r)(p.alterPartial({
+          Module(new GroundTestTile(resetSignal = r)(p.alterPartial({
             case TLId => "L1toL2"
             case GroundTestId => i
             case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0
@@ -56,6 +56,7 @@ class WithGroundTest extends Config(
     }
     case UseFPU => false
     case UseAtomics => false
+    case UseCompressed => false
     case _ => throw new CDEMatchError
   })
 
@@ -165,20 +166,30 @@ class WithNastiConverterTest extends Config(
 
 class WithUnitTest extends Config(
   (pname, site, here) => pname match {
-    case GroundTestKey => Seq.fill(site(NTiles)) { GroundTestTileSettings() }
-    case BuildGroundTest =>
-      (p: Parameters) => Module(new UnitTestSuite()(p))
-    case UnitTests => (testParams: Parameters) => {
-      implicit val p = testParams
-      Seq(
-        Module(new MultiWidthFifoTest),
-        Module(new SmiConverterTest),
-        Module(new AtosConverterTest),
-        Module(new NastiMemoryDemuxTest),
-        Module(new ROMSlaveTest),
-        Module(new TileLinkRAMTest),
-        Module(new HastiTest))
+    case BuildTiles => {
+      val groundtest = if (site(XLen) == 64)
+        DefaultTestSuites.groundtest64
+      else
+        DefaultTestSuites.groundtest32
+      TestGeneration.addSuite(groundtest("p"))
+      TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
+      (0 until site(NTiles)).map { i =>
+        (r: Bool, p: Parameters) => {
+          Module(new UnitTestTile(resetSignal = r)(p.alterPartial({
+            case TLId => "L1toL2"
+            case NCachedTileLinkPorts => 0
+            case NUncachedTileLinkPorts => 0
+            case RoccNCSRs => 0
+          })))
+        }
+      }
     }
+    case UnitTests => (testParams: Parameters) =>
+      JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams)
+    case NMemoryChannels => Dump("N_MEM_CHANNELS", 0)
+    case UseFPU => false
+    case UseAtomics => false
+    case UseCompressed => false
     case _ => throw new CDEMatchError
   })
 
@@ -249,7 +260,7 @@ class FancyNastiConverterTestConfig extends Config(
   new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
   new WithL2Cache ++ new GroundTestConfig)
 
-class UnitTestConfig extends Config(new WithUnitTest ++ new GroundTestConfig)
+class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
 
 class TraceGenConfig extends Config(
   new WithNCores(2) ++ new WithTraceGen ++ new GroundTestConfig)

src/main/scala/UnitTest.scala

@@ -0,0 +1,16 @@
+package rocketchip
+
+import Chisel._
+import junctions.unittests.UnitTestSuite
+import rocket.Tile
+import cde.Parameters
+
+class UnitTestTile(clockSignal: Clock = null, resetSignal: Bool = null)
+    (implicit p: Parameters) extends Tile(clockSignal, resetSignal)(p) {
+
+  require(io.cached.size == 0)
+  require(io.uncached.size == 0)
+
+  val tests = Module(new UnitTestSuite)
+  when (tests.io.finished) { stop() }
+}

uncore/src/main/scala/unittests/Drivers.scala

@@ -1,4 +1,4 @@
-package groundtest.unittests
+package uncore.unittests
 
 import Chisel._
 import junctions._

uncore/src/main/scala/unittests/Tests.scala

@@ -1,12 +1,11 @@
-package groundtest.unittests
-
+package uncore.unittests
 
 import Chisel._
 import junctions._
+import junctions.unittests._
 import uncore.devices._
 import uncore.tilelink._
 import uncore.converters._
-import groundtest.common._
 import cde.Parameters
 
 class SmiConverterTest(implicit val p: Parameters) extends UnitTest
@@ -76,3 +75,11 @@ class TileLinkRAMTest(implicit val p: Parameters)
   driver.io.start := io.start
   io.finished := driver.io.finished
 }
+
+object UncoreUnitTests {
+  def apply(implicit p: Parameters): Seq[UnitTest] =
+    Seq(
+      Module(new SmiConverterTest),
+      Module(new ROMSlaveTest),
+      Module(new TileLinkRAMTest))
+}