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make unit tests local to the packages being tested

This commit is contained in:
Howard Mao 2016-08-01 16:05:24 -07:00
parent 98eede0505
commit b7723f1ff8
18 changed files with 136 additions and 106 deletions

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@ -4,7 +4,6 @@ import Chisel._
import uncore.tilelink._ import uncore.tilelink._
import uncore.constants._ import uncore.constants._
import uncore.agents._ import uncore.agents._
import groundtest.common._
import cde.{Parameters, Field} import cde.{Parameters, Field}
class CacheFillTest(implicit p: Parameters) extends GroundTest()(p) class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)

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@ -5,7 +5,6 @@ import uncore.tilelink._
import uncore.constants._ import uncore.constants._
import junctions._ import junctions._
import rocket._ import rocket._
import groundtest.common._
import scala.util.Random import scala.util.Random
import cde.{Parameters, Field} import cde.{Parameters, Field}

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@ -6,7 +6,6 @@ import uncore.devices.NTiles
import uncore.constants._ import uncore.constants._
import junctions._ import junctions._
import rocket._ import rocket._
import groundtest.common._
import scala.util.Random import scala.util.Random
import cde.{Parameters, Field} import cde.{Parameters, Field}

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@ -4,7 +4,6 @@ import Chisel._
import uncore.tilelink._ import uncore.tilelink._
import uncore.converters._ import uncore.converters._
import junctions._ import junctions._
import groundtest.common._
import cde.Parameters import cde.Parameters
class NastiGenerator(id: Int)(implicit val p: Parameters) extends Module class NastiGenerator(id: Int)(implicit val p: Parameters) extends Module

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@ -4,9 +4,8 @@ import Chisel._
import uncore.tilelink._ import uncore.tilelink._
import uncore.constants._ import uncore.constants._
import uncore.agents._ import uncore.agents._
import junctions.{ParameterizedBundle, HasAddrMapParameters} import junctions.{ParameterizedBundle, HasAddrMapParameters, Timer}
import rocket.HellaCacheIO import rocket.HellaCacheIO
import groundtest.common._
import cde.{Parameters, Field} import cde.{Parameters, Field}
class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p) { class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p) {

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@ -1,4 +1,4 @@
package groundtest.common package groundtest
import Chisel._ import Chisel._
import rocket._ import rocket._

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@ -22,7 +22,6 @@ import uncore.constants._
import uncore.devices.NTiles import uncore.devices.NTiles
import junctions._ import junctions._
import rocket._ import rocket._
import groundtest.common._
import scala.util.Random import scala.util.Random
import cde.{Parameters, Field} import cde.{Parameters, Field}

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@ -1,56 +1,7 @@
package groundtest.common package groundtest
import Chisel._ import Chisel._
// ============
// Static timer
// ============
// Timer with a statically-specified period.
// Can take multiple inflight start-stop events with ID
// Will continue to count down as long as at least one event is inflight
class Timer(initCount: Int, maxInflight: Int) extends Module {
val io = new Bundle {
val start = Valid(UInt(width = log2Up(maxInflight))).flip
val stop = Valid(UInt(width = log2Up(maxInflight))).flip
val timeout = Valid(UInt(width = log2Up(maxInflight)))
}
val inflight = Reg(init = Vec.fill(maxInflight) { Bool(false) })
val countdown = Reg(UInt(width = log2Up(initCount)))
val active = inflight.reduce(_ || _)
when (active) {
countdown := countdown - UInt(1)
}
when (io.start.valid) {
inflight(io.start.bits) := Bool(true)
countdown := UInt(initCount - 1)
}
when (io.stop.valid) {
inflight(io.stop.bits) := Bool(false)
}
io.timeout.valid := countdown === UInt(0) && active
io.timeout.bits := PriorityEncoder(inflight)
assert(!io.stop.valid || inflight(io.stop.bits),
"Timer stop for transaction that's not inflight")
}
object Timer {
def apply(initCount: Int, start: Bool, stop: Bool): Bool = {
val timer = Module(new Timer(initCount, 1))
timer.io.start.valid := start
timer.io.start.bits := UInt(0)
timer.io.stop.valid := stop
timer.io.stop.bits := UInt(0)
timer.io.timeout.valid
}
}
// ============= // =============
// Dynamic timer // Dynamic timer
// ============= // =============

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@ -1,9 +1,8 @@
package groundtest.unittests package junctions.unittests
import Chisel._ import Chisel._
import junctions._ import junctions._
import junctions.NastiConstants._ import junctions.NastiConstants._
import groundtest.common._
import cde.Parameters import cde.Parameters
class NastiDriver(dataWidth: Int, burstLen: Int, nBursts: Int) class NastiDriver(dataWidth: Int, burstLen: Int, nBursts: Int)
@ -76,12 +75,6 @@ class NastiDriver(dataWidth: Int, burstLen: Int, nBursts: Int)
assert(!io.nasti.r.valid || read_data === expected_data, assert(!io.nasti.r.valid || read_data === expected_data,
s"NastiDriver got wrong data") s"NastiDriver got wrong data")
val ar_timeout = Timer(1024, io.nasti.ar.fire(), io.nasti.r.fire())
val aw_timeout = Timer(1024, io.nasti.aw.fire(), io.nasti.b.fire())
assert(!ar_timeout && !aw_timeout,
s"NastiDriver for $name timed out")
} }

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@ -1,4 +1,4 @@
package groundtest.unittests package junctions.unittests
import Chisel._ import Chisel._
import junctions._ import junctions._

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@ -1,4 +1,4 @@
package groundtest.unittests package junctions.unittests
import Chisel._ import Chisel._
import junctions._ import junctions._

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@ -1,13 +1,7 @@
package groundtest.unittests package junctions.unittests
import Chisel._ import Chisel._
import junctions._ import junctions._
import junctions.NastiConstants._
import uncore.tilelink._
import uncore.converters._
import uncore.constants._
import uncore.devices._
import groundtest.common._
import cde.{Field, Parameters} import cde.{Field, Parameters}
abstract class UnitTest extends Module { abstract class UnitTest extends Module {
@ -23,7 +17,11 @@ abstract class UnitTest extends Module {
case object UnitTests extends Field[Parameters => Seq[UnitTest]] case object UnitTests extends Field[Parameters => Seq[UnitTest]]
class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) { class UnitTestSuite(implicit p: Parameters) extends Module {
val io = new Bundle {
val finished = Bool(OUTPUT)
}
val tests = p(UnitTests)(p) val tests = p(UnitTests)(p)
val s_idle :: s_start :: s_wait :: s_done :: Nil = Enum(Bits(), 4) val s_idle :: s_start :: s_wait :: s_done :: Nil = Enum(Bits(), 4)
@ -39,17 +37,27 @@ class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {
state := Mux(test_idx === UInt(tests.size - 1), s_done, s_start) state := Mux(test_idx === UInt(tests.size - 1), s_done, s_start)
} }
io.status.timeout.valid := Bool(false) val timer = Module(new Timer(1000, tests.size))
tests.zipWithIndex.foreach { case (mod, i) => tests.zipWithIndex.foreach { case (mod, i) =>
mod.io.start := (state === s_start) && test_idx === UInt(i) mod.io.start := (state === s_start) && test_idx === UInt(i)
val timeout = Timer(1000, mod.io.start, mod.io.finished) when (test_idx === UInt(i)) {
assert(!timeout, s"UnitTest ${mod.getClass.getSimpleName} timed out") timer.io.start.valid := mod.io.start
when (timeout) { timer.io.start.bits := UInt(i)
io.status.timeout.valid := Bool(true) timer.io.stop.valid := mod.io.finished
io.status.timeout.bits := UInt(i) timer.io.stop.bits := UInt(i)
} }
} }
io.status.finished := (state === s_done) io.finished := (state === s_done)
io.status.error.valid := Bool(false)
assert(!timer.io.timeout.valid, "UnitTest timed out")
}
object JunctionsUnitTests {
def apply(implicit p: Parameters): Seq[UnitTest] =
Seq(
Module(new MultiWidthFifoTest),
Module(new AtosConverterTest),
Module(new NastiMemoryDemuxTest),
Module(new HastiTest))
} }

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@ -312,3 +312,54 @@ class MultiWidthFifo(inW: Int, outW: Int, n: Int) extends Module {
io.in.ready := size < UInt(n * nBeats) io.in.ready := size < UInt(n * nBeats)
} }
} }
// ============
// Static timer
// ============
// Timer with a statically-specified period.
// Can take multiple inflight start-stop events with ID
// Will continue to count down as long as at least one event is inflight
class Timer(initCount: Int, maxInflight: Int) extends Module {
val io = new Bundle {
val start = Valid(UInt(width = log2Up(maxInflight))).flip
val stop = Valid(UInt(width = log2Up(maxInflight))).flip
val timeout = Valid(UInt(width = log2Up(maxInflight)))
}
val inflight = Reg(init = Vec.fill(maxInflight) { Bool(false) })
val countdown = Reg(UInt(width = log2Up(initCount)))
val active = inflight.reduce(_ || _)
when (active) {
countdown := countdown - UInt(1)
}
when (io.start.valid) {
inflight(io.start.bits) := Bool(true)
countdown := UInt(initCount - 1)
}
when (io.stop.valid) {
inflight(io.stop.bits) := Bool(false)
}
io.timeout.valid := countdown === UInt(0) && active
io.timeout.bits := PriorityEncoder(inflight)
assert(!io.stop.valid || inflight(io.stop.bits),
"Timer stop for transaction that's not inflight")
}
object Timer {
def apply(initCount: Int, start: Bool, stop: Bool): Bool = {
val timer = Module(new Timer(initCount, 1))
timer.io.start.valid := start
timer.io.start.bits := UInt(0)
timer.io.stop.valid := stop
timer.io.stop.bits := UInt(0)
timer.io.timeout.valid
}
}

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@ -3,7 +3,6 @@ package rocketchip
import Chisel._ import Chisel._
import cde.{Parameters, Field} import cde.{Parameters, Field}
import groundtest._ import groundtest._
import groundtest.common._
import uncore.tilelink._ import uncore.tilelink._
import uncore.agents._ import uncore.agents._

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@ -2,14 +2,14 @@ package rocketchip
import Chisel._ import Chisel._
import groundtest._ import groundtest._
import groundtest.unittests._
import groundtest.common._
import rocket._ import rocket._
import uncore.tilelink._ import uncore.tilelink._
import uncore.coherence._ import uncore.coherence._
import uncore.agents._ import uncore.agents._
import uncore.devices.NTiles import uncore.devices.NTiles
import uncore.unittests._
import junctions._ import junctions._
import junctions.unittests._
import scala.collection.mutable.LinkedHashSet import scala.collection.mutable.LinkedHashSet
import cde.{Parameters, Config, Dump, Knob, CDEMatchError} import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
import scala.math.max import scala.math.max
@ -44,7 +44,7 @@ class WithGroundTest extends Config(
(0 until site(NTiles)).map { i => (0 until site(NTiles)).map { i =>
val tileSettings = site(GroundTestKey)(i) val tileSettings = site(GroundTestKey)(i)
(r: Bool, p: Parameters) => { (r: Bool, p: Parameters) => {
Module(new GroundTestTile(r)(p.alterPartial({ Module(new GroundTestTile(resetSignal = r)(p.alterPartial({
case TLId => "L1toL2" case TLId => "L1toL2"
case GroundTestId => i case GroundTestId => i
case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0 case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0
@ -56,6 +56,7 @@ class WithGroundTest extends Config(
} }
case UseFPU => false case UseFPU => false
case UseAtomics => false case UseAtomics => false
case UseCompressed => false
case _ => throw new CDEMatchError case _ => throw new CDEMatchError
}) })
@ -165,20 +166,30 @@ class WithNastiConverterTest extends Config(
class WithUnitTest extends Config( class WithUnitTest extends Config(
(pname, site, here) => pname match { (pname, site, here) => pname match {
case GroundTestKey => Seq.fill(site(NTiles)) { GroundTestTileSettings() } case BuildTiles => {
case BuildGroundTest => val groundtest = if (site(XLen) == 64)
(p: Parameters) => Module(new UnitTestSuite()(p)) DefaultTestSuites.groundtest64
case UnitTests => (testParams: Parameters) => { else
implicit val p = testParams DefaultTestSuites.groundtest32
Seq( TestGeneration.addSuite(groundtest("p"))
Module(new MultiWidthFifoTest), TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
Module(new SmiConverterTest), (0 until site(NTiles)).map { i =>
Module(new AtosConverterTest), (r: Bool, p: Parameters) => {
Module(new NastiMemoryDemuxTest), Module(new UnitTestTile(resetSignal = r)(p.alterPartial({
Module(new ROMSlaveTest), case TLId => "L1toL2"
Module(new TileLinkRAMTest), case NCachedTileLinkPorts => 0
Module(new HastiTest)) case NUncachedTileLinkPorts => 0
case RoccNCSRs => 0
})))
} }
}
}
case UnitTests => (testParams: Parameters) =>
JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams)
case NMemoryChannels => Dump("N_MEM_CHANNELS", 0)
case UseFPU => false
case UseAtomics => false
case UseCompressed => false
case _ => throw new CDEMatchError case _ => throw new CDEMatchError
}) })
@ -249,7 +260,7 @@ class FancyNastiConverterTestConfig extends Config(
new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++ new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
new WithL2Cache ++ new GroundTestConfig) new WithL2Cache ++ new GroundTestConfig)
class UnitTestConfig extends Config(new WithUnitTest ++ new GroundTestConfig) class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
class TraceGenConfig extends Config( class TraceGenConfig extends Config(
new WithNCores(2) ++ new WithTraceGen ++ new GroundTestConfig) new WithNCores(2) ++ new WithTraceGen ++ new GroundTestConfig)

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@ -0,0 +1,16 @@
package rocketchip
import Chisel._
import junctions.unittests.UnitTestSuite
import rocket.Tile
import cde.Parameters
class UnitTestTile(clockSignal: Clock = null, resetSignal: Bool = null)
(implicit p: Parameters) extends Tile(clockSignal, resetSignal)(p) {
require(io.cached.size == 0)
require(io.uncached.size == 0)
val tests = Module(new UnitTestSuite)
when (tests.io.finished) { stop() }
}

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@ -1,4 +1,4 @@
package groundtest.unittests package uncore.unittests
import Chisel._ import Chisel._
import junctions._ import junctions._

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@ -1,12 +1,11 @@
package groundtest.unittests package uncore.unittests
import Chisel._ import Chisel._
import junctions._ import junctions._
import junctions.unittests._
import uncore.devices._ import uncore.devices._
import uncore.tilelink._ import uncore.tilelink._
import uncore.converters._ import uncore.converters._
import groundtest.common._
import cde.Parameters import cde.Parameters
class SmiConverterTest(implicit val p: Parameters) extends UnitTest class SmiConverterTest(implicit val p: Parameters) extends UnitTest
@ -76,3 +75,11 @@ class TileLinkRAMTest(implicit val p: Parameters)
driver.io.start := io.start driver.io.start := io.start
io.finished := driver.io.finished io.finished := driver.io.finished
} }
object UncoreUnitTests {
def apply(implicit p: Parameters): Seq[UnitTest] =
Seq(
Module(new SmiConverterTest),
Module(new ROMSlaveTest),
Module(new TileLinkRAMTest))
}