riscv/rocket-chip
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PutBlock bugfix

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This commit is contained in:
Henry Cook
2015-03-16 00:09:55 -07:00
parent f6d1a2fb76
commit b72230a9f0
1 changed files with 1 additions and 1 deletions
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2
uncore/src/main/scala/cache.scala
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@@ -636,7 +636,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
val offset = xact.addr_byte()(byteAddrBits-1, log2Up(amoAluOperandBits/8))
amoalu.io.lhs := old_data >> offset*amoOpSz
amoalu.io.rhs := new_data >> offset*amoOpSz
val valid_beat = xact.addr_beat === beat
val valid_beat = xact.is(Acquire.putBlockType) || xact.addr_beat === beat
val wmask = Fill(dataBits, valid_beat) &
Mux(xact.is(Acquire.putAtomicType),
FillInterleaved(amoAluOperandBits, UIntToOH(offset)),