riscv/rocket-chip
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This commit is contained in:
Henry Cook 2013-05-01 10:24:36 -07:00
parent 722bc917d3
commit b6945408cb
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -1014,7 +1014,7 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
// nack it like it's hot // nack it like it's hot
val s1_nack = dtlb.io.req.valid && dtlb.io.resp.miss || val s1_nack = dtlb.io.req.valid && dtlb.io.resp.miss ||
s1_req.addr(indexmsb,indexlsb) === prober.io.meta_write.bits.idx && !prober.io.req.ready || s1_req.addr(indexmsb,indexlsb) === prober.io.meta_write.bits.idx && !prober.io.req.ready ||
s1_req.addr(tagmsb, indexlsb) === io.mem.probe.bits.payload.addr && io.mem.probe.fire() s1_req.addr >> conf.offbits === io.mem.probe.bits.payload.addr && io.mem.probe.fire()
val s2_nack_hit = RegEn(s1_nack, s1_valid || s1_replay) val s2_nack_hit = RegEn(s1_nack, s1_valid || s1_replay)
when (s2_nack_hit) { mshr.io.req.valid := Bool(false) } when (s2_nack_hit) { mshr.io.req.valid := Bool(false) }
val s2_nack_victim = s2_hit && mshr.io.secondary_miss val s2_nack_victim = s2_hit && mshr.io.secondary_miss