riscv/rocket-chip
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Merge pull request #1039 from freechipsproject/tile-crossing-params

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Improvements wrt connecting RocketTiles to SystemBus
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Henry Cook authored and GitHub committed 2017-10-11 17:12:03 -07:00
2 parents 024ccd8ac2 60934ac622
commit b64609bfe8
16 files changed
+276 -119
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src/main/scala/system/Configs.scala
+1 -1
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@@ -66,7 +66,7 @@ class DualCoreConfig extends Config(
class TinyConfig extends Config(
new WithNMemoryChannels(0) ++
new WithStatelessBridge ++
new WithNTinyCores(1) ++
new With1TinyCore ++
new BaseConfig)