riscv/rocket-chip
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util: augment String and use to name couplers

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This commit is contained in:
Henry Cook
2018-02-20 17:09:30 -08:00
parent a6d3965491
commit b617e26c13
6 changed files with 64 additions and 38 deletions
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10
src/main/scala/subsystem/FrontBus.scala
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@@ -13,7 +13,7 @@ case class FrontBusParams(beatBytes: Int, blockBytes: Int) extends HasTLBusParam
case object FrontBusKey extends Field[FrontBusParams]
class FrontBus(params: FrontBusParams, val crossing: SubsystemClockCrossing = SynchronousCrossing())
(implicit p: Parameters) extends TLBusWrapper(params, "FrontBus")
(implicit p: Parameters) extends TLBusWrapper(params, "front_bus")
with HasTLXbarPhy
with HasCrossing {
@@ -21,7 +21,7 @@ class FrontBus(params: FrontBusParams, val crossing: SubsystemClockCrossing = Sy
name: Option[String] = None,
buffers: Int = 1)
(gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle]): InwardNodeHandle[D,U,E,B] = {
from(s"Port${name.getOrElse("")}") {
from("port" named name) {
val nodes = TLFIFOFixer(TLFIFOFixer.all) +: TLBuffer.chain(buffers)
inwardNode :=* nodes.reduce(_ :=* _) :=* gen
}
@@ -29,18 +29,18 @@ class FrontBus(params: FrontBusParams, val crossing: SubsystemClockCrossing = Sy
def fromMaster(name: Option[String] = None, buffers: Int = 1)
(gen: => TLNode): TLInwardNode = {
from(s"Master${name.getOrElse("")}") {
from("master" named name) {
inwardNode :=* TLBuffer.chain(buffers).reduce(_ :=* _) :=* gen
}
}
def fromCoherentChip(gen: => TLNode): TLInwardNode = {
from("CoherentChip") { inwardNode :=* gen }
from("coherent_subsystem") { inwardNode :=* gen }
}
def toSystemBus(buffer: BufferParams = BufferParams.none)
(gen: => TLInwardNode) {
to("SystemBus") { gen :*= TLBuffer(buffer) :*= outwardNode }
to("sbus") { gen :=* TLBuffer(buffer) :=* outwardNode }
}
}

8
src/main/scala/subsystem/MemoryBus.scala
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@@ -41,7 +41,7 @@ case class MemoryBusParams(beatBytes: Int, blockBytes: Int) extends HasTLBusPara
case object MemoryBusKey extends Field[MemoryBusParams]
/** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */
class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "MemoryBus")(p)
class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "memory_bus")(p)
with HasTLXbarPhy {
private def bufferTo(buffer: BufferParams): TLOutwardNode =
@@ -51,7 +51,7 @@ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWr
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLInwardNode = {
from(s"CoherenceManager${name.getOrElse("")}") {
from("coherence_manager" named name) {
inwardNode :*= TLBuffer(buffer) :*= gen
}
}
@@ -60,14 +60,14 @@ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWr
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = {
to(s"DRAMController${name.getOrElse("")}") { gen := bufferTo(buffer) }
to("memory_controller" named name) { gen := bufferTo(buffer) }
}
def toVariableWidthSlave(
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = {
to(s"Slave${name.getOrElse("")}") {
to("slave" named name) {
gen :*= TLFragmenter(params.beatBytes, params.blockBytes) :*= bufferTo(buffer)
}
}

21
src/main/scala/subsystem/PeripheryBus.scala
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@@ -6,6 +6,7 @@ import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
case class PeripheryBusParams(
beatBytes: Int,
@@ -16,7 +17,7 @@ case class PeripheryBusParams(
case object PeripheryBusKey extends Field[PeripheryBusParams]
class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCrossing = SynchronousCrossing())
(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus")
(implicit p: Parameters) extends TLBusWrapper(params, "periphery_bus")
with HasTLXbarPhy
with HasCrossing {
@@ -36,14 +37,14 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = {
to(s"Slave${name.getOrElse("")}") { gen :*= bufferTo(buffer) }
to("slave" named name) { gen :*= bufferTo(buffer) }
}
def toVariableWidthSlave(
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = {
to(s"Slave${name.getOrElse("")}") {
to("slave" named name) {
gen :*= fragmentTo(params.beatBytes, params.blockBytes, buffer)
}
}
@@ -52,9 +53,7 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = {
to(s"Slave${name.getOrElse("")}") {
gen :*= fixedWidthTo(buffer)
}
to("slave" named name) { gen :*= fixedWidthTo(buffer) }
}
def toFixedWidthSingleBeatSlave(
@@ -62,7 +61,7 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = {
to(s"Slave${name.getOrElse("")}") {
to("slave" named name) {
gen :*= TLFragmenter(widthBytes, params.blockBytes) :*= fixedWidthTo(buffer)
}
}
@@ -72,7 +71,7 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = {
to(s"Slave${name.getOrElse("")}") {
to("slave" named name) {
gen :*= fragmentTo(params.beatBytes, maxXferBytes, buffer)
}
}
@@ -81,7 +80,7 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
arithmetic: Boolean = true,
buffer: BufferParams = BufferParams.default)
(gen: => TLOutwardNode) {
from("SystemBus") {
from("sbus") {
(inwardNode
:*= TLBuffer(buffer)
:*= TLAtomicAutomata(arithmetic = arithmetic)
@@ -93,7 +92,7 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLInwardNode = {
from(s"OtherMaster${name.getOrElse("")}") { inwardNode :*= TLBuffer(buffer) :*= gen }
from("master" named name) { inwardNode :*= TLBuffer(buffer) :*= gen }
}
@@ -101,7 +100,7 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
name: Option[String] = None,
buffers: Int = 0)
(gen: => TLNode): TLOutwardNode = {
to(s"Tile${name.getOrElse("")}") {
to("tile" named name) {
FlipRendering { implicit p =>
gen :*= bufferTo(buffers)
}

23
src/main/scala/subsystem/Ports.scala
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@@ -31,6 +31,7 @@ trait HasMasterAXI4MemPort extends HasMemoryBus {
val module: HasMasterAXI4MemPortModuleImp
private val params = p(ExtMem)
private val portName = "axi4"
private val device = new MemoryDevice
val mem_axi4 = AXI4SlaveNode(Seq.tabulate(nMemoryChannels) { channel =>
@@ -50,7 +51,7 @@ trait HasMasterAXI4MemPort extends HasMemoryBus {
})
memBuses.map { m =>
mem_axi4 := m.toDRAMController(Some("AXI4DRAM")) {
mem_axi4 := m.toDRAMController(Some(portName)) {
(AXI4UserYanker() := AXI4IdIndexer(params.idBits) := TLToAXI4())
}
}
@@ -80,7 +81,8 @@ trait HasMasterAXI4MemPortModuleImp extends LazyModuleImp with HasMasterAXI4MemP
/** Adds a AXI4 port to the system intended to master an MMIO device bus */
trait HasMasterAXI4MMIOPort extends HasSystemBus {
private val params = p(ExtBus)
private val device = new SimpleBus("mmio", Nil)
private val portName = "mmio_port_axi4"
private val device = new SimpleBus(portName.kebab, Nil)
val mmio_axi4 = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = AddressSet.misaligned(params.base, params.size),
@@ -90,7 +92,7 @@ trait HasMasterAXI4MMIOPort extends HasSystemBus {
supportsRead = TransferSizes(1, params.maxXferBytes))),
beatBytes = params.beatBytes)))
mmio_axi4 := sbus.toFixedWidthPort(Some("AXI4MMIO")) {
mmio_axi4 := sbus.toFixedWidthPort(Some(portName)) {
(AXI4Buffer()
:= AXI4UserYanker()
:= AXI4Deinterleaver(sbus.blockBytes)
@@ -119,13 +121,14 @@ trait HasMasterAXI4MMIOPortModuleImp extends LazyModuleImp with HasMasterAXI4MMI
/** Adds an AXI4 port to the system intended to be a slave on an MMIO device bus */
trait HasSlaveAXI4Port extends HasSystemBus {
private val params = p(ExtIn)
private val portName = "slave_port_axi4"
val l2FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
masters = Seq(AXI4MasterParameters(
name = "AXI4 periphery",
name = portName.kebab,
id = IdRange(0, 1 << params.idBits))))))
private val fifoBits = 1
sbus.fromPort(Some("AXI4Front")) {
sbus.fromPort(Some(portName)) {
(TLWidthWidget(params.beatBytes)
:= AXI4ToTL()
:= AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1)))
@@ -159,7 +162,8 @@ trait HasSlaveAXI4PortModuleImp extends LazyModuleImp with HasSlaveAXI4PortBundl
/** Adds a TileLink port to the system intended to master an MMIO device bus */
trait HasMasterTLMMIOPort extends HasSystemBus {
private val params = p(ExtBus)
private val device = new SimpleBus("mmio", Nil)
private val portName = "mmio_port_tl"
private val device = new SimpleBus(portName.kebab, Nil)
val mmio_tl = TLManagerNode(Seq(TLManagerPortParameters(
managers = Seq(TLManagerParameters(
address = AddressSet.misaligned(params.base, params.size),
@@ -170,7 +174,7 @@ trait HasMasterTLMMIOPort extends HasSystemBus {
supportsPutPartial = TransferSizes(1, sbus.blockBytes))),
beatBytes = params.beatBytes)))
mmio_tl := sbus.toFixedWidthPort(Some("TLMMIO")) {
mmio_tl := sbus.toFixedWidthPort(Some(portName)) {
TLBuffer() := TLSourceShrinker(1 << params.idBits)
}
}
@@ -202,12 +206,13 @@ trait HasMasterTLMMIOPortModuleImp extends LazyModuleImp with HasMasterTLMMIOPor
*/
trait HasSlaveTLPort extends HasSystemBus {
private val params = p(ExtIn)
private val portName = "slave_port_tl"
val l2FrontendTLNode = TLClientNode(Seq(TLClientPortParameters(
clients = Seq(TLClientParameters(
name = "Front Port (TL)",
name = portName.kebab,
sourceId = IdRange(0, 1 << params.idBits))))))
sbus.fromPort(Some("TLFront")) {
sbus.fromPort(Some(portName)) {
TLSourceShrinker(1 << params.sourceBits) := TLWidthWidget(params.beatBytes)
} := l2FrontendTLNode
}

18
src/main/scala/subsystem/SystemBus.scala
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@@ -12,7 +12,7 @@ case class SystemBusParams(beatBytes: Int, blockBytes: Int) extends HasTLBusPara
case object SystemBusKey extends Field[SystemBusParams]
class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "SystemBus")
class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "system_bus")
with HasTLXbarPhy {
private val master_splitter = LazyModule(new TLSplitter)
@@ -25,7 +25,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def toPeripheryBus(buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = {
to("PeripheryBus") {
to("pbus") {
(gen
:= TLFIFOFixer(TLFIFOFixer.all)
:= TLWidthWidget(params.beatBytes)
@@ -34,24 +34,24 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
}
def toMemoryBus(gen: => TLInwardNode) {
to("MemoryBus") { gen :*= delayNode :*= outwardNode }
to("mbus") { gen :*= delayNode :*= outwardNode }
}
def toSlave(name: Option[String] = None, buffer: BufferParams = BufferParams.default)
(gen: => TLNode): TLOutwardNode = {
to(s"Slave${name.getOrElse("")}") { gen :*= bufferTo(buffer) }
to("slave" named name) { gen :*= bufferTo(buffer) }
}
def toSplitSlave(name: Option[String] = None)
(gen: => TLNode): TLOutwardNode = {
to(s"Slave${name.getOrElse("")}") { gen :*= master_splitter.node }
to("slave" named name) { gen :*= master_splitter.node }
}
def toVariableWidthSlave(
name: Option[String] = None,
buffer: BufferParams = BufferParams.default)
(gen: => TLNode): TLOutwardNode = {
to(s"Slave${name.getOrElse("")}") {
to("slave" named name) {
gen :*= TLFragmenter(params.beatBytes, params.blockBytes) :*= bufferTo(buffer)
}
}
@@ -69,7 +69,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
buffers: Int = 0,
cork: Option[Boolean] = None)
(gen: => TLNode): TLInwardNode = {
from(s"Tile${name.getOrElse("")}") {
from("tile" named name) {
(List(master_splitter.node, TLFIFOFixer(TLFIFOFixer.allUncacheable)) ++ TLBuffer.chain(buffers))
.reduce(_ :=* _) :=* gen
}
@@ -79,7 +79,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
name: Option[String] = None,
buffer: BufferParams = BufferParams.default)
(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = {
to(s"Port${name.getOrElse("")}") {
to("port" named name) {
gen := TLWidthWidget(params.beatBytes) := bufferTo(buffer)
}
}
@@ -88,7 +88,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
name: Option[String] = None,
buffers: Int = 0)
(gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle]): InwardNodeHandle[D,U,E,B] = {
from(s"Port${name.getOrElse("")}") {
from("port" named name) {
(List(
master_splitter.node,
TLFIFOFixer(TLFIFOFixer.all)) ++

22
src/main/scala/util/package.scala
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@@ -43,6 +43,28 @@ package object util {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value