riscv/rocket-chip
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4-way associative by default

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This commit is contained in:
Henry Cook 2012-03-14 17:51:12 -07:00
parent 7dde7099d2
commit b5fa86e844
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/consts.scala
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@ -177,7 +177,7 @@ object Constants
val LG_REFILL_WIDTH = 4; // log2(cache bus width in bytes)
val IDX_BITS = 7;
val TAG_BITS = PADDR_BITS - OFFSET_BITS - IDX_BITS;
val NWAYS = 1;
val NWAYS = 4
require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS);
// coherence parameters