riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

4-way associative by default

Browse Source
This commit is contained in:
Henry Cook 2012-03-14 17:51:12 -07:00
parent 7dde7099d2
commit b5fa86e844
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/consts.scala
View File

@ -177,7 +177,7 @@ object Constants
val LG_REFILL_WIDTH = 4; // log2(cache bus width in bytes) val LG_REFILL_WIDTH = 4; // log2(cache bus width in bytes)
val IDX_BITS = 7; val IDX_BITS = 7;
val TAG_BITS = PADDR_BITS - OFFSET_BITS - IDX_BITS; val TAG_BITS = PADDR_BITS - OFFSET_BITS - IDX_BITS;
val NWAYS = 1; val NWAYS = 4
require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS); require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS);
// coherence parameters // coherence parameters