riscv/rocket-chip
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regmapper: eliminate race condition in RegisterCrossing bypass

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This commit is contained in:
Wesley W. Terpstra
2016-10-07 11:45:20 -07:00
parent f250426728
commit b5f5ef69c1
2 changed files with 93 additions and 81 deletions
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22
src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
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@ -229,20 +229,18 @@ trait RRTest1Module extends Module with HasRegMap
val field = UInt(width = bits)
val readCross = Module(new RegisterReadCrossing(field))
readCross.io.master_clock := clock
readCross.io.master_reset := reset
readCross.io.master_allow := Bool(true)
readCross.io.slave_clock := clocks.io.clock_out
readCross.io.slave_reset := reset
readCross.io.slave_allow := Bool(true)
readCross.io.master_clock := clock
readCross.io.master_reset := reset
readCross.io.master_bypass := Bool(false)
readCross.io.slave_clock := clocks.io.clock_out
readCross.io.slave_reset := reset
val writeCross = Module(new RegisterWriteCrossing(field))
writeCross.io.master_clock := clock
writeCross.io.master_reset := reset
writeCross.io.master_allow := Bool(true)
writeCross.io.slave_clock := clocks.io.clock_out
writeCross.io.slave_reset := reset
writeCross.io.slave_allow := Bool(true)
writeCross.io.master_clock := clock
writeCross.io.master_reset := reset
writeCross.io.master_bypass := Bool(false)
writeCross.io.slave_clock := clocks.io.clock_out
writeCross.io.slave_reset := reset
readCross.io.slave_register := writeCross.io.slave_register
RegField(bits, readCross.io.master_port, writeCross.io.master_port)