register_crossing: Remove the need for AsyncScope by specifying the master clock and reset. (#393)
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@ -4,7 +4,7 @@ package regmapper
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import Chisel._
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import chisel3.util.{Irrevocable}
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import util.{AsyncQueue,AsyncScope,AsyncResetRegVec}
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import util.{AsyncQueue,AsyncResetRegVec}
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// A very simple flow control state machine, run in the specified clock domain
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class BusyRegisterCrossing(clock: Clock, reset: Bool)
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@ -143,7 +143,10 @@ class RegisterReadCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
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object AsyncRWSlaveRegField {
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def apply(slave_clock: Clock,
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def apply(
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master_clock: Clock,
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master_reset: Bool,
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slave_clock: Clock,
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slave_reset: Bool,
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width: Int,
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init: Int,
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@ -160,10 +163,8 @@ object AsyncRWSlaveRegField {
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val wr_crossing = Module (new RegisterWriteCrossing(UInt(width = width)))
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name.foreach(n => wr_crossing.suggestName(s"${n}_wcrossing"))
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val scope = Module (new AsyncScope())
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wr_crossing.io.master_clock := scope.clock
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wr_crossing.io.master_reset := scope.reset
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wr_crossing.io.master_clock := master_clock
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wr_crossing.io.master_reset := master_reset
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wr_crossing.io.master_allow := master_allow
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wr_crossing.io.slave_clock := slave_clock
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wr_crossing.io.slave_reset := slave_reset
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@ -175,8 +176,8 @@ object AsyncRWSlaveRegField {
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val rd_crossing = Module (new RegisterReadCrossing(UInt(width = width )))
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name.foreach(n => rd_crossing.suggestName(s"${n}_rcrossing"))
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rd_crossing.io.master_clock := scope.clock
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rd_crossing.io.master_reset := scope.reset
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rd_crossing.io.master_clock := master_clock
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rd_crossing.io.master_reset := master_reset
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rd_crossing.io.master_allow := master_allow
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rd_crossing.io.slave_clock := slave_clock
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rd_crossing.io.slave_reset := slave_reset
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