riscv/rocket-chip
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Periphery: dynamically create address map + config string for TL2

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This commit is contained in:
Wesley W. Terpstra
2016-09-16 17:27:49 -07:00
parent 8876d83640
commit b5ce6150c7
3 changed files with 26 additions and 22 deletions
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24
src/main/scala/rocketchip/Utils.scala
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@ -8,6 +8,7 @@ import uncore.devices._
import rocket._
import rocket.Util._
import coreplex._
import uncore.tilelink2._
import java.nio.file.{Files, Paths}
import java.nio.{ByteBuffer, ByteOrder}
@ -51,7 +52,7 @@ class GlobalVariable[T] {
}
object GenerateGlobalAddrMap {
def apply(p: Parameters, pDevicesEntries: Seq[AddrMapEntry]) = {
def apply(p: Parameters, pDevicesEntries: Seq[AddrMapEntry], peripheryManagers: Seq[TLManagerParameters]) = {
lazy val intIOAddrMap: AddrMap = {
val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
@ -64,8 +65,20 @@ object GenerateGlobalAddrMap {
new AddrMap(entries)
}
lazy val tl2AddrMap = new AddrMap(pDevicesEntries, collapse = true)
lazy val extIOAddrMap = new AddrMap(AddrMapEntry("TL2", tl2AddrMap) +: p(ExtMMIOPorts), collapse = true)
lazy val tl2Devices = peripheryManagers.map { manager =>
val attr = MemAttr(
(if (manager.supportsGet) AddrMapProt.R else 0) |
(if (manager.supportsPutFull) AddrMapProt.W else 0) |
(if (manager.executable) AddrMapProt.X else 0))
val name = manager.nodePath.last.lazyModule.name // !!!
manager.address.zipWithIndex.map { case (address, i) =>
require (!address.strided) // TL1 can't do this
AddrMapEntry(s"${name}", MemRange(address.base, address.mask+1, attr))
}
}.flatten
lazy val tl2AddrMap = new AddrMap(tl2Devices, collapse = true)
lazy val extIOAddrMap = new AddrMap(AddrMapEntry("TL2", tl2AddrMap) +: (p(ExtMMIOPorts) ++ pDevicesEntries), collapse = true)
val memBase = 0x80000000L
val memSize = p(ExtMemSize)
@ -80,7 +93,7 @@ object GenerateGlobalAddrMap {
}
object GenerateConfigString {
def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry]) = {
def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry], peripheryManagers: Seq[TLManagerParameters]) = {
val addrMap = p(GlobalAddrMap)
val plicAddr = addrMap("io:int:plic").start
val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:ext:TL2:clint").start)
@ -136,12 +149,13 @@ object GenerateConfigString {
}
res append "};\n"
pDevicesEntries foreach { entry =>
val region = addrMap("io:ext:TL2:" + entry.name)
val region = addrMap("io:ext:" + entry.name)
res append s"${entry.name} {\n"
res append s" addr 0x${region.start.toString(16)};\n"
res append s" size 0x${region.size.toString(16)}; \n"
res append "}\n"
}
peripheryManagers.foreach { manager => res append manager.dts }
res append '\u0000'
res.toString
}