riscv/rocket-chip
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Periphery: dynamically create address map + config string for TL2

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This commit is contained in:
Wesley W. Terpstra
2016-09-16 17:27:49 -07:00
parent 8876d83640
commit b5ce6150c7
3 changed files with 26 additions and 22 deletions
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14
src/main/scala/rocketchip/Periphery.scala
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@ -289,10 +289,6 @@ trait PeripheryCoreplexLocalInterrupter extends LazyModule with HasPeripheryPara
val clint = LazyModule(new CoreplexLocalInterrupter(clintConfig)(innerMMIOParams))
// The periphery bus is 32-bit, so we may need to adapt its width to XLen
clint.node := TLFragmenter(TLWidthWidget(peripheryBus.node, 4), beatBytes, 256)
// TL1 legacy
val pDevices: ResourceManager[AddrMapEntry]
pDevices.add(AddrMapEntry("clint", MemRange(clintConfig.address, clintConfig.size, MemAttr(AddrMapProt.RW))))
}
trait PeripheryCoreplexLocalInterrupterBundle {
@ -315,12 +311,8 @@ trait PeripheryBootROM extends LazyModule {
implicit val p: Parameters
val peripheryBus: TLXbar
val rom = LazyModule(new TLROM(0x1000, 0x1000, GenerateBootROM(p)))
val rom = LazyModule(new TLROM(0x1000, 0x1000, GenerateBootROM(p)) { override def name = "bootrom" })
rom.node := TLFragmenter(peripheryBus.node, 4, 256)
// TL1 legacy address map
val pDevices: ResourceManager[AddrMapEntry]
pDevices.add(AddrMapEntry("bootrom", MemRange(0x1000, 4096, MemAttr(AddrMapProt.RX))))
}
trait PeripheryBootROMBundle {
@ -344,10 +336,6 @@ trait PeripheryTestRAM extends LazyModule {
val sram = LazyModule(new TLRAM(AddressSet(ramBase, ramSize-1)))
sram.node := TLFragmenter(peripheryBus.node, 4, 256)
// TL1 legacy address map
val pDevices: ResourceManager[AddrMapEntry]
pDevices.add(AddrMapEntry("testram", MemRange(ramBase, ramSize, MemAttr(AddrMapProt.RW))))
}
trait PeripheryTestRAMBundle {