changed val names in hub to match new tilelink names
This commit is contained in:
Henry Cook
parent
c211d74e95
commit
b5ccdab514
@ -24,14 +24,14 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex
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val p_data = (new PipeIO) { new TrackerProbeData }.flip
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val can_alloc = Bool(INPUT)
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val grant_ack = Bool(INPUT)
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val p_rep_cnt_dec = Bits(INPUT, conf.ln.nTiles)
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val p_req_cnt_inc = Bits(INPUT, conf.ln.nTiles)
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val release_cnt_dec = Bits(INPUT, conf.ln.nTiles)
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val probe_cnt_inc = Bits(INPUT, conf.ln.nTiles)
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val tile_incoherent = Bits(INPUT, conf.ln.nTiles)
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val p_rep_data = (new PipeIO) { new ReleaseData }.flip
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val x_init_data = (new PipeIO) { new AcquireData }.flip
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val release_data = (new PipeIO) { new ReleaseData }.flip
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val acquire_data = (new PipeIO) { new AcquireData }.flip
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val sent_grant_ack = Bool(INPUT)
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val p_rep_data_dep = (new PipeIO) { new TrackerDependency }.flip
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val x_init_data_dep = (new PipeIO) { new TrackerDependency }.flip
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val release_data_dep = (new PipeIO) { new TrackerDependency }.flip
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val acquire_data_dep = (new PipeIO) { new TrackerDependency }.flip
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val mem_req_cmd = (new FIFOIO) { new MemReqCmd }
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val mem_req_data = (new FIFOIO) { new MemData }
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@ -40,17 +40,17 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex
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val busy = Bool(OUTPUT)
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val addr = Bits(OUTPUT, PADDR_BITS - OFFSET_BITS)
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val init_client_id = Bits(OUTPUT, conf.ln.idBits)
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val p_rep_client_id = Bits(OUTPUT, conf.ln.idBits)
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val release_client_id = Bits(OUTPUT, conf.ln.idBits)
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val client_xact_id = Bits(OUTPUT, CLIENT_XACT_ID_BITS)
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val sharer_count = Bits(OUTPUT, conf.ln.idBits+1)
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val a_type = Bits(OUTPUT, ACQUIRE_TYPE_MAX_BITS)
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val push_p_req = Bits(OUTPUT, conf.ln.nTiles)
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val pop_p_rep = Bits(OUTPUT, conf.ln.nTiles)
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val pop_p_rep_data = Bits(OUTPUT, conf.ln.nTiles)
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val pop_p_rep_dep = Bits(OUTPUT, conf.ln.nTiles)
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val pop_x_init = Bits(OUTPUT, conf.ln.nTiles)
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val pop_x_init_data = Bits(OUTPUT, conf.ln.nTiles)
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val pop_x_init_dep = Bits(OUTPUT, conf.ln.nTiles)
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val push_probe = Bits(OUTPUT, conf.ln.nTiles)
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val pop_release = Bits(OUTPUT, conf.ln.nTiles)
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val pop_release_data = Bits(OUTPUT, conf.ln.nTiles)
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val pop_release_dep = Bits(OUTPUT, conf.ln.nTiles)
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val pop_acquire = Bits(OUTPUT, conf.ln.nTiles)
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val pop_acquire_data = Bits(OUTPUT, conf.ln.nTiles)
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val pop_acquire_dep = Bits(OUTPUT, conf.ln.nTiles)
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val send_grant_ack = Bool(OUTPUT)
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}
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@ -91,19 +91,19 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex
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val state = Reg(resetVal = s_idle)
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val xact = Reg{ new Acquire }
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val init_client_id_ = Reg{ Bits() }
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val p_rep_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
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val p_req_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles))
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val p_rep_client_id_ = Reg{ Bits() }
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val release_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
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val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles))
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val release_client_id_ = Reg{ Bits() }
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val x_needs_read = Reg(resetVal = Bool(false))
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val x_init_data_needs_write = Reg(resetVal = Bool(false))
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val p_rep_data_needs_write = Reg(resetVal = Bool(false))
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val acquire_data_needs_write = Reg(resetVal = Bool(false))
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val release_data_needs_write = Reg(resetVal = Bool(false))
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val x_w_mem_cmd_sent = Reg(resetVal = Bool(false))
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val p_w_mem_cmd_sent = Reg(resetVal = Bool(false))
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val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
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val mem_cnt_next = mem_cnt + UFix(1)
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val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES))
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val p_req_initial_flags = Bits(width = conf.ln.nTiles)
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p_req_initial_flags := Bits(0)
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val probe_initial_flags = Bits(width = conf.ln.nTiles)
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probe_initial_flags := Bits(0)
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if (conf.ln.nTiles > 1) {
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// issue self-probes for uncached read xacts to facilitate I$ coherence
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// TODO: this is hackish; figure out how to do it more systematically
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@ -112,13 +112,13 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex
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case _ => Bool(false)
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}
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val myflag = Mux(probe_self, Bits(0), UFixToOH(io.alloc_req.bits.client_id(log2Up(conf.ln.nTiles)-1,0)))
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p_req_initial_flags := ~(io.tile_incoherent | myflag)
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probe_initial_flags := ~(io.tile_incoherent | myflag)
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}
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io.busy := state != s_idle
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io.addr := xact.addr
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io.init_client_id := init_client_id_
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io.p_rep_client_id := p_rep_client_id_
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io.release_client_id := release_client_id_
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io.client_xact_id := xact.client_xact_id
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io.sharer_count := UFix(conf.ln.nTiles) // TODO: Broadcast only
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io.a_type := xact.a_type
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@ -134,13 +134,13 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex
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io.probe.bits.p_type := co.getProbeType(xact.a_type, UFix(0))
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io.probe.bits.master_xact_id := UFix(id)
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io.probe.bits.addr := xact.addr
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io.push_p_req := Bits(0, width = conf.ln.nTiles)
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io.pop_p_rep := Bits(0, width = conf.ln.nTiles)
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io.pop_p_rep_data := Bits(0, width = conf.ln.nTiles)
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io.pop_p_rep_dep := Bits(0, width = conf.ln.nTiles)
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io.pop_x_init := Bits(0, width = conf.ln.nTiles)
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io.pop_x_init_data := Bits(0, width = conf.ln.nTiles)
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io.pop_x_init_dep := Bits(0, width = conf.ln.nTiles)
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io.push_probe := Bits(0, width = conf.ln.nTiles)
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io.pop_release := Bits(0, width = conf.ln.nTiles)
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io.pop_release_data := Bits(0, width = conf.ln.nTiles)
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io.pop_release_dep := Bits(0, width = conf.ln.nTiles)
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io.pop_acquire := Bits(0, width = conf.ln.nTiles)
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io.pop_acquire_data := Bits(0, width = conf.ln.nTiles)
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io.pop_acquire_dep := Bits(0, width = conf.ln.nTiles)
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io.send_grant_ack := Bool(false)
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switch (state) {
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@ -148,62 +148,62 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex
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when( io.alloc_req.valid && io.can_alloc ) {
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xact := io.alloc_req.bits.acquire
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init_client_id_ := io.alloc_req.bits.client_id
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x_init_data_needs_write := co.messageHasData(io.alloc_req.bits.acquire)
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acquire_data_needs_write := co.messageHasData(io.alloc_req.bits.acquire)
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x_needs_read := co.needsMemRead(io.alloc_req.bits.acquire.a_type, UFix(0))
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p_req_flags := p_req_initial_flags
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probe_flags := probe_initial_flags
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mem_cnt := UFix(0)
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p_w_mem_cmd_sent := Bool(false)
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x_w_mem_cmd_sent := Bool(false)
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io.pop_x_init := UFix(1) << io.alloc_req.bits.client_id
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io.pop_acquire := UFix(1) << io.alloc_req.bits.client_id
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if(conf.ln.nTiles > 1) {
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p_rep_count := PopCount(p_req_initial_flags)
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state := Mux(p_req_initial_flags.orR, s_probe, s_mem)
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release_count := PopCount(probe_initial_flags)
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state := Mux(probe_initial_flags.orR, s_probe, s_mem)
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} else state := s_mem
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}
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}
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is(s_probe) {
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when(p_req_flags.orR) {
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io.push_p_req := p_req_flags
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when(probe_flags.orR) {
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io.push_probe := probe_flags
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io.probe.valid := Bool(true)
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}
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when(io.p_req_cnt_inc.orR) {
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p_req_flags := p_req_flags & ~io.p_req_cnt_inc // unflag sent reqs
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when(io.probe_cnt_inc.orR) {
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probe_flags := probe_flags & ~io.probe_cnt_inc // unflag sent reqs
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}
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when(io.p_rep_cnt_dec.orR) {
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val dec = PopCount(io.p_rep_cnt_dec)
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io.pop_p_rep := io.p_rep_cnt_dec
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if(conf.ln.nTiles > 1) p_rep_count := p_rep_count - dec
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when(p_rep_count === dec) {
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when(io.release_cnt_dec.orR) {
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val dec = PopCount(io.release_cnt_dec)
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io.pop_release := io.release_cnt_dec
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if(conf.ln.nTiles > 1) release_count := release_count - dec
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when(release_count === dec) {
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state := s_mem
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}
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}
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when(io.p_data.valid) {
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p_rep_data_needs_write := Bool(true)
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p_rep_client_id_ := io.p_data.bits.client_id
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release_data_needs_write := Bool(true)
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release_client_id_ := io.p_data.bits.client_id
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}
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}
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is(s_mem) {
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when (p_rep_data_needs_write) {
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when (release_data_needs_write) {
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doMemReqWrite(io.mem_req_cmd,
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io.mem_req_data,
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io.mem_req_lock,
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io.p_rep_data,
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p_rep_data_needs_write,
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io.release_data,
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release_data_needs_write,
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p_w_mem_cmd_sent,
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io.pop_p_rep_data,
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io.pop_p_rep_dep,
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io.p_rep_data_dep.valid && (io.p_rep_data_dep.bits.master_xact_id === UFix(id)),
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p_rep_client_id_)
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} . elsewhen(x_init_data_needs_write) {
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io.pop_release_data,
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io.pop_release_dep,
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io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(id)),
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release_client_id_)
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} . elsewhen(acquire_data_needs_write) {
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doMemReqWrite(io.mem_req_cmd,
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io.mem_req_data,
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io.mem_req_lock,
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io.x_init_data,
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x_init_data_needs_write,
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io.acquire_data,
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acquire_data_needs_write,
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x_w_mem_cmd_sent,
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io.pop_x_init_data,
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io.pop_x_init_dep,
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io.x_init_data_dep.valid && (io.x_init_data_dep.bits.master_xact_id === UFix(id)),
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io.pop_acquire_data,
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io.pop_acquire_dep,
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io.acquire_data_dep.valid && (io.acquire_data_dep.bits.master_xact_id === UFix(id)),
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init_client_id_)
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} . elsewhen (x_needs_read) {
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doMemReqRead(io.mem_req_cmd, x_needs_read)
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@ -274,22 +274,22 @@ class CoherenceHubNull(implicit conf: CoherenceHubConfiguration) extends Coheren
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{
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val co = conf.co.asInstanceOf[ThreeStateIncoherence]
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val x_init = io.tiles(0).acquire
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val is_write = x_init.bits.payload.a_type === co.acquireWriteback
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x_init.ready := io.mem.req_cmd.ready && !(is_write && io.mem.resp.valid) //stall write req/resp to handle previous read resp
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io.mem.req_cmd.valid := x_init.valid && !(is_write && io.mem.resp.valid)
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val acquire = io.tiles(0).acquire
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val is_write = acquire.bits.payload.a_type === co.acquireWriteback
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acquire.ready := io.mem.req_cmd.ready && !(is_write && io.mem.resp.valid) //stall write req/resp to handle previous read resp
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io.mem.req_cmd.valid := acquire.valid && !(is_write && io.mem.resp.valid)
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io.mem.req_cmd.bits.rw := is_write
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io.mem.req_cmd.bits.tag := x_init.bits.payload.client_xact_id
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io.mem.req_cmd.bits.addr := x_init.bits.payload.addr
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io.mem.req_cmd.bits.tag := acquire.bits.payload.client_xact_id
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io.mem.req_cmd.bits.addr := acquire.bits.payload.addr
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io.mem.req_data <> io.tiles(0).acquire_data
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val grant = io.tiles(0).grant
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grant.bits.payload.g_type := Mux(io.mem.resp.valid, co.grantData, co.grantAck)
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grant.bits.payload.client_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, x_init.bits.payload.client_xact_id)
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grant.bits.payload.client_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, acquire.bits.payload.client_xact_id)
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grant.bits.payload.master_xact_id := UFix(0) // don't care
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grant.bits.payload.data := io.mem.resp.bits.data
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grant.bits.payload.require_ack := Bool(true)
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grant.valid := io.mem.resp.valid || x_init.valid && is_write && io.mem.req_cmd.ready
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grant.valid := io.mem.resp.valid || acquire.valid && is_write && io.mem.req_cmd.ready
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io.tiles(0).abort.valid := Bool(false)
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io.tiles(0).grant_ack.ready := Bool(true)
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@ -314,8 +314,8 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
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val send_grant_ack_arr = Vec(NGLOBAL_XACTS){ Bool() }
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val do_free_arr = Vec(NGLOBAL_XACTS){ Bool() }
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val p_rep_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nTiles){ Bool()} }
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val p_req_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nTiles){ Bool()} }
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val release_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nTiles){ Bool()} }
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val probe_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nTiles){ Bool()} }
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val sent_grant_ack_arr = Vec(NGLOBAL_XACTS){ Bool() }
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val p_data_client_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=conf.ln.idBits) }
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val p_data_valid_arr = Vec(NGLOBAL_XACTS){ Bool() }
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@ -332,8 +332,8 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
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t.grant_ack := do_free_arr(i)
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t.p_data.bits.client_id := p_data_client_id_arr(i)
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t.p_data.valid := p_data_valid_arr(i)
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t.p_rep_cnt_dec := p_rep_cnt_dec_arr(i).toBits
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t.p_req_cnt_inc := p_req_cnt_inc_arr(i).toBits
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t.release_cnt_dec := release_cnt_dec_arr(i).toBits
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t.probe_cnt_inc := probe_cnt_inc_arr(i).toBits
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t.tile_incoherent := io.incoherent.toBits
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t.sent_grant_ack := sent_grant_ack_arr(i)
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do_free_arr(i) := Bool(false)
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@ -341,21 +341,21 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
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p_data_client_id_arr(i) := Bits(0, width = conf.ln.idBits)
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p_data_valid_arr(i) := Bool(false)
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for( j <- 0 until conf.ln.nTiles) {
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p_rep_cnt_dec_arr(i)(j) := Bool(false)
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p_req_cnt_inc_arr(i)(j) := Bool(false)
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release_cnt_dec_arr(i)(j) := Bool(false)
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probe_cnt_inc_arr(i)(j) := Bool(false)
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}
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}
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val p_rep_data_dep_list = List.fill(conf.ln.nTiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY
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val x_init_data_dep_list = List.fill(conf.ln.nTiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY
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val release_data_dep_list = List.fill(conf.ln.nTiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY
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val acquire_data_dep_list = List.fill(conf.ln.nTiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY
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// Free finished transactions
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for( j <- 0 until conf.ln.nTiles ) {
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val finish = io.tiles(j).grant_ack
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when (finish.valid) {
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do_free_arr(finish.bits.payload.master_xact_id) := Bool(true)
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val ack = io.tiles(j).grant_ack
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when (ack.valid) {
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do_free_arr(ack.bits.payload.master_xact_id) := Bool(true)
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}
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finish.ready := Bool(true)
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ack.ready := Bool(true)
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}
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// Reply to initial requestor
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@ -402,31 +402,31 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
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// Handle probe replies, which may or may not have data
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for( j <- 0 until conf.ln.nTiles ) {
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val p_rep = io.tiles(j).release
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val p_rep_data = io.tiles(j).release_data
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val idx = p_rep.bits.payload.master_xact_id
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val pop_p_reps = trackerList.map(_.io.pop_p_rep(j).toBool)
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val do_pop = foldR(pop_p_reps)(_ || _)
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p_rep.ready := Bool(true)
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p_rep_data_dep_list(j).io.enq.valid := p_rep.valid && co.messageHasData(p_rep.bits.payload)
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p_rep_data_dep_list(j).io.enq.bits.master_xact_id := p_rep.bits.payload.master_xact_id
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p_rep_data.ready := foldR(trackerList.map(_.io.pop_p_rep_data(j)))(_ || _)
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when (p_rep.valid && co.messageHasData(p_rep.bits.payload)) {
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val release = io.tiles(j).release
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val release_data = io.tiles(j).release_data
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val idx = release.bits.payload.master_xact_id
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val pop_releases = trackerList.map(_.io.pop_release(j).toBool)
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val do_pop = foldR(pop_releases)(_ || _)
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release.ready := Bool(true)
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release_data_dep_list(j).io.enq.valid := release.valid && co.messageHasData(release.bits.payload)
|
||||
release_data_dep_list(j).io.enq.bits.master_xact_id := release.bits.payload.master_xact_id
|
||||
release_data.ready := foldR(trackerList.map(_.io.pop_release_data(j)))(_ || _)
|
||||
when (release.valid && co.messageHasData(release.bits.payload)) {
|
||||
p_data_valid_arr(idx) := Bool(true)
|
||||
p_data_client_id_arr(idx) := UFix(j)
|
||||
}
|
||||
p_rep_data_dep_list(j).io.deq.ready := foldR(trackerList.map(_.io.pop_p_rep_dep(j).toBool))(_||_)
|
||||
release_data_dep_list(j).io.deq.ready := foldR(trackerList.map(_.io.pop_release_dep(j).toBool))(_||_)
|
||||
}
|
||||
for( i <- 0 until NGLOBAL_XACTS ) {
|
||||
trackerList(i).io.p_rep_data.valid := io.tiles(trackerList(i).io.p_rep_client_id).release_data.valid
|
||||
trackerList(i).io.p_rep_data.bits := io.tiles(trackerList(i).io.p_rep_client_id).release_data.bits.payload
|
||||
trackerList(i).io.release_data.valid := io.tiles(trackerList(i).io.release_client_id).release_data.valid
|
||||
trackerList(i).io.release_data.bits := io.tiles(trackerList(i).io.release_client_id).release_data.bits.payload
|
||||
|
||||
trackerList(i).io.p_rep_data_dep.valid := MuxLookup(trackerList(i).io.p_rep_client_id, p_rep_data_dep_list(0).io.deq.valid, (0 until conf.ln.nTiles).map( j => UFix(j) -> p_rep_data_dep_list(j).io.deq.valid))
|
||||
trackerList(i).io.p_rep_data_dep.bits := MuxLookup(trackerList(i).io.p_rep_client_id, p_rep_data_dep_list(0).io.deq.bits, (0 until conf.ln.nTiles).map( j => UFix(j) -> p_rep_data_dep_list(j).io.deq.bits))
|
||||
trackerList(i).io.release_data_dep.valid := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.valid, (0 until conf.ln.nTiles).map( j => UFix(j) -> release_data_dep_list(j).io.deq.valid))
|
||||
trackerList(i).io.release_data_dep.bits := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.bits, (0 until conf.ln.nTiles).map( j => UFix(j) -> release_data_dep_list(j).io.deq.bits))
|
||||
|
||||
for( j <- 0 until conf.ln.nTiles) {
|
||||
val p_rep = io.tiles(j).release
|
||||
p_rep_cnt_dec_arr(i)(j) := p_rep.valid && (p_rep.bits.payload.master_xact_id === UFix(i))
|
||||
val release = io.tiles(j).release
|
||||
release_cnt_dec_arr(i)(j) := release.valid && (release.bits.payload.master_xact_id === UFix(i))
|
||||
}
|
||||
}
|
||||
|
||||
@ -435,31 +435,31 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
|
||||
val abort_state_arr = Vec(conf.ln.nTiles) { Reg(resetVal = s_idle) }
|
||||
val want_to_abort_arr = Vec(conf.ln.nTiles) { Bool() }
|
||||
for( j <- 0 until conf.ln.nTiles ) {
|
||||
val x_init = io.tiles(j).acquire
|
||||
val x_init_data = io.tiles(j).acquire_data
|
||||
val acquire = io.tiles(j).acquire
|
||||
val acquire_data = io.tiles(j).acquire_data
|
||||
val x_abort = io.tiles(j).abort
|
||||
val abort_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
|
||||
val conflicts = Vec(NGLOBAL_XACTS) { Bool() }
|
||||
for( i <- 0 until NGLOBAL_XACTS) {
|
||||
val t = trackerList(i).io
|
||||
conflicts(i) := t.busy && x_init.valid && co.isCoherenceConflict(t.addr, x_init.bits.payload.addr)
|
||||
conflicts(i) := t.busy && acquire.valid && co.isCoherenceConflict(t.addr, acquire.bits.payload.addr)
|
||||
}
|
||||
x_abort.bits.payload.client_xact_id := x_init.bits.payload.client_xact_id
|
||||
want_to_abort_arr(j) := x_init.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && co.messageHasData(x_init.bits.payload)))
|
||||
x_abort.bits.payload.client_xact_id := acquire.bits.payload.client_xact_id
|
||||
want_to_abort_arr(j) := acquire.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!acquire_data_dep_list(j).io.enq.ready && co.messageHasData(acquire.bits.payload)))
|
||||
|
||||
x_abort.valid := Bool(false)
|
||||
switch(abort_state_arr(j)) {
|
||||
is(s_idle) {
|
||||
when(want_to_abort_arr(j)) {
|
||||
when(co.messageHasData(x_init.bits.payload)) {
|
||||
when(co.messageHasData(acquire.bits.payload)) {
|
||||
abort_state_arr(j) := s_abort_drain
|
||||
} . otherwise {
|
||||
abort_state_arr(j) := s_abort_send
|
||||
}
|
||||
}
|
||||
}
|
||||
is(s_abort_drain) { // raises x_init_data.ready below
|
||||
when(x_init_data.valid) {
|
||||
is(s_abort_drain) { // raises acquire_data.ready below
|
||||
when(acquire_data.valid) {
|
||||
abort_cnt := abort_cnt + UFix(1)
|
||||
when(abort_cnt === ~UFix(0, width = log2Up(REFILL_CYCLES))) {
|
||||
abort_state_arr(j) := s_abort_send
|
||||
@ -468,7 +468,7 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
|
||||
}
|
||||
is(s_abort_send) { // nothing is dequeued for now
|
||||
x_abort.valid := Bool(true)
|
||||
when(x_abort.ready) { // raises x_init.ready below
|
||||
when(x_abort.ready) { // raises acquire.ready below
|
||||
abort_state_arr(j) := s_idle
|
||||
}
|
||||
}
|
||||
@ -486,41 +486,41 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
|
||||
trackerList(i).io.alloc_req.bits := init_arb.io.out.bits
|
||||
trackerList(i).io.alloc_req.valid := init_arb.io.out.valid
|
||||
|
||||
trackerList(i).io.x_init_data.bits := io.tiles(trackerList(i).io.init_client_id).acquire_data.bits.payload
|
||||
trackerList(i).io.x_init_data.valid := io.tiles(trackerList(i).io.init_client_id).acquire_data.valid
|
||||
trackerList(i).io.x_init_data_dep.bits := MuxLookup(trackerList(i).io.init_client_id, x_init_data_dep_list(0).io.deq.bits, (0 until conf.ln.nTiles).map( j => UFix(j) -> x_init_data_dep_list(j).io.deq.bits))
|
||||
trackerList(i).io.x_init_data_dep.valid := MuxLookup(trackerList(i).io.init_client_id, x_init_data_dep_list(0).io.deq.valid, (0 until conf.ln.nTiles).map( j => UFix(j) -> x_init_data_dep_list(j).io.deq.valid))
|
||||
trackerList(i).io.acquire_data.bits := io.tiles(trackerList(i).io.init_client_id).acquire_data.bits.payload
|
||||
trackerList(i).io.acquire_data.valid := io.tiles(trackerList(i).io.init_client_id).acquire_data.valid
|
||||
trackerList(i).io.acquire_data_dep.bits := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.bits, (0 until conf.ln.nTiles).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.bits))
|
||||
trackerList(i).io.acquire_data_dep.valid := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.valid, (0 until conf.ln.nTiles).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.valid))
|
||||
}
|
||||
for( j <- 0 until conf.ln.nTiles ) {
|
||||
val x_init = io.tiles(j).acquire
|
||||
val x_init_data = io.tiles(j).acquire_data
|
||||
val x_init_data_dep = x_init_data_dep_list(j).io.deq
|
||||
val acquire = io.tiles(j).acquire
|
||||
val acquire_data = io.tiles(j).acquire_data
|
||||
val acquire_data_dep = acquire_data_dep_list(j).io.deq
|
||||
val x_abort = io.tiles(j).abort
|
||||
init_arb.io.in(j).valid := (abort_state_arr(j) === s_idle) && !want_to_abort_arr(j) && x_init.valid
|
||||
init_arb.io.in(j).bits.acquire := x_init.bits.payload
|
||||
init_arb.io.in(j).valid := (abort_state_arr(j) === s_idle) && !want_to_abort_arr(j) && acquire.valid
|
||||
init_arb.io.in(j).bits.acquire := acquire.bits.payload
|
||||
init_arb.io.in(j).bits.client_id := UFix(j)
|
||||
val pop_x_inits = trackerList.map(_.io.pop_x_init(j).toBool)
|
||||
val do_pop = foldR(pop_x_inits)(_||_)
|
||||
x_init_data_dep_list(j).io.enq.valid := do_pop && co.messageHasData(x_init.bits.payload) && (abort_state_arr(j) === s_idle)
|
||||
x_init_data_dep_list(j).io.enq.bits.master_xact_id := OHToUFix(pop_x_inits)
|
||||
x_init.ready := (x_abort.valid && x_abort.ready) || do_pop
|
||||
x_init_data.ready := (abort_state_arr(j) === s_abort_drain) || foldR(trackerList.map(_.io.pop_x_init_data(j).toBool))(_||_)
|
||||
x_init_data_dep.ready := foldR(trackerList.map(_.io.pop_x_init_dep(j).toBool))(_||_)
|
||||
val pop_acquires = trackerList.map(_.io.pop_acquire(j).toBool)
|
||||
val do_pop = foldR(pop_acquires)(_||_)
|
||||
acquire_data_dep_list(j).io.enq.valid := do_pop && co.messageHasData(acquire.bits.payload) && (abort_state_arr(j) === s_idle)
|
||||
acquire_data_dep_list(j).io.enq.bits.master_xact_id := OHToUFix(pop_acquires)
|
||||
acquire.ready := (x_abort.valid && x_abort.ready) || do_pop
|
||||
acquire_data.ready := (abort_state_arr(j) === s_abort_drain) || foldR(trackerList.map(_.io.pop_acquire_data(j).toBool))(_||_)
|
||||
acquire_data_dep.ready := foldR(trackerList.map(_.io.pop_acquire_dep(j).toBool))(_||_)
|
||||
}
|
||||
|
||||
alloc_arb.io.out.ready := init_arb.io.out.valid
|
||||
|
||||
// Handle probe request generation
|
||||
// Must arbitrate for each request port
|
||||
val p_req_arb_arr = List.fill(conf.ln.nTiles)((new Arbiter(NGLOBAL_XACTS)) { new Probe() })
|
||||
val probe_arb_arr = List.fill(conf.ln.nTiles)((new Arbiter(NGLOBAL_XACTS)) { new Probe() })
|
||||
for( j <- 0 until conf.ln.nTiles ) {
|
||||
for( i <- 0 until NGLOBAL_XACTS ) {
|
||||
val t = trackerList(i).io
|
||||
p_req_arb_arr(j).io.in(i).bits := t.probe.bits
|
||||
p_req_arb_arr(j).io.in(i).valid := t.probe.valid && t.push_p_req(j)
|
||||
p_req_cnt_inc_arr(i)(j) := p_req_arb_arr(j).io.in(i).ready
|
||||
probe_arb_arr(j).io.in(i).bits := t.probe.bits
|
||||
probe_arb_arr(j).io.in(i).valid := t.probe.valid && t.push_probe(j)
|
||||
probe_cnt_inc_arr(i)(j) := probe_arb_arr(j).io.in(i).ready
|
||||
}
|
||||
FIFOedLogicalNetworkIOWrapper(p_req_arb_arr(j).io.out) <> io.tiles(j).probe
|
||||
FIFOedLogicalNetworkIOWrapper(probe_arb_arr(j).io.out) <> io.tiles(j).probe
|
||||
}
|
||||
|
||||
}
|
||||
@ -538,8 +538,8 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren
|
||||
implicit val lnConf = conf.ln
|
||||
val co = conf.co
|
||||
val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
|
||||
val p_rep_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth must >= NPRIMARY
|
||||
val x_init_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth should >= NPRIMARY
|
||||
val release_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth must >= NPRIMARY
|
||||
val acquire_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth should >= NPRIMARY
|
||||
|
||||
for( i <- 0 until NGLOBAL_XACTS ) {
|
||||
val t = trackerList(i)
|
||||
@ -552,49 +552,49 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren
|
||||
// Handle transaction initiation requests
|
||||
// Only one allocation per cycle
|
||||
// Init requests may or may not have data
|
||||
val x_init = io.network.acquire
|
||||
val x_init_data = io.network.acquire_data
|
||||
val acquire = io.network.acquire
|
||||
val acquire_data = io.network.acquire_data
|
||||
val x_abort = io.network.abort
|
||||
val x_dep_deq = x_init_data_dep_q.io.deq
|
||||
val x_dep_deq = acquire_data_dep_q.io.deq
|
||||
val s_idle :: s_abort_drain :: s_abort_send :: Nil = Enum(3){ UFix() }
|
||||
val abort_state = Reg(resetVal = s_idle)
|
||||
val abort_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
|
||||
val any_conflict = trackerList.map(_.io.has_conflict).reduce(_||_)
|
||||
val all_busy = trackerList.map(_.io.busy).reduce(_&&_)
|
||||
val want_to_abort = x_init.valid && (any_conflict || all_busy || (!x_init_data_dep_q.io.enq.ready && co.messageHasData(x_init.bits.payload)))
|
||||
val want_to_abort = acquire.valid && (any_conflict || all_busy || (!acquire_data_dep_q.io.enq.ready && co.messageHasData(acquire.bits.payload)))
|
||||
|
||||
val alloc_arb = (new Arbiter(NGLOBAL_XACTS)) { Bool() }
|
||||
for( i <- 0 until NGLOBAL_XACTS ) {
|
||||
alloc_arb.io.in(i).valid := !trackerList(i).io.busy
|
||||
trackerList(i).io.x_init.bits := x_init.bits
|
||||
trackerList(i).io.x_init.valid := (abort_state === s_idle) && !want_to_abort && x_init.valid && alloc_arb.io.in(i).ready
|
||||
trackerList(i).io.acquire.bits := acquire.bits
|
||||
trackerList(i).io.acquire.valid := (abort_state === s_idle) && !want_to_abort && acquire.valid && alloc_arb.io.in(i).ready
|
||||
|
||||
trackerList(i).io.x_init_data.bits := x_init_data.bits
|
||||
trackerList(i).io.x_init_data.valid := x_init_data.valid
|
||||
trackerList(i).io.x_init_data_dep.bits := x_dep_deq.bits
|
||||
trackerList(i).io.x_init_data_dep.valid := x_dep_deq.valid
|
||||
trackerList(i).io.acquire_data.bits := acquire_data.bits
|
||||
trackerList(i).io.acquire_data.valid := acquire_data.valid
|
||||
trackerList(i).io.acquire_data_dep.bits := x_dep_deq.bits
|
||||
trackerList(i).io.acquire_data_dep.valid := x_dep_deq.valid
|
||||
}
|
||||
val pop_x_init = trackerList.map(_.io.x_init.ready).reduce(_||_)
|
||||
x_init.ready := (x_abort.valid && x_abort.ready) || pop_x_init
|
||||
x_init_data.ready := (abort_state === s_abort_drain) || trackerList.map(_.io.x_init_data.ready).reduce(_||_)
|
||||
x_init_data_dep_q.io.enq.valid := pop_x_init && co.messageHasData(x_init.bits.payload) && (abort_state === s_idle)
|
||||
x_init_data_dep_q.io.enq.bits.master_xact_id := OHToUFix(trackerList.map(_.io.x_init.ready))
|
||||
x_dep_deq.ready := trackerList.map(_.io.x_init_data_dep.ready).reduce(_||_)
|
||||
val pop_acquire = trackerList.map(_.io.acquire.ready).reduce(_||_)
|
||||
acquire.ready := (x_abort.valid && x_abort.ready) || pop_acquire
|
||||
acquire_data.ready := (abort_state === s_abort_drain) || trackerList.map(_.io.acquire_data.ready).reduce(_||_)
|
||||
acquire_data_dep_q.io.enq.valid := pop_acquire && co.messageHasData(acquire.bits.payload) && (abort_state === s_idle)
|
||||
acquire_data_dep_q.io.enq.bits.master_xact_id := OHToUFix(trackerList.map(_.io.acquire.ready))
|
||||
x_dep_deq.ready := trackerList.map(_.io.acquire_data_dep.ready).reduce(_||_)
|
||||
|
||||
alloc_arb.io.out.ready := x_init.valid
|
||||
alloc_arb.io.out.ready := acquire.valid
|
||||
|
||||
// Nack conflicting transaction init attempts
|
||||
x_abort.bits.header.dst := x_init.bits.header.src
|
||||
x_abort.bits.payload.client_xact_id := x_init.bits.payload.client_xact_id
|
||||
x_abort.bits.header.dst := acquire.bits.header.src
|
||||
x_abort.bits.payload.client_xact_id := acquire.bits.payload.client_xact_id
|
||||
x_abort.valid := Bool(false)
|
||||
switch(abort_state) {
|
||||
is(s_idle) {
|
||||
when(want_to_abort) {
|
||||
abort_state := Mux( co.messageHasData(x_init.bits.payload), s_abort_drain, s_abort_send)
|
||||
abort_state := Mux( co.messageHasData(acquire.bits.payload), s_abort_drain, s_abort_send)
|
||||
}
|
||||
}
|
||||
is(s_abort_drain) { // raises x_init_data.ready below
|
||||
when(x_init_data.valid) {
|
||||
is(s_abort_drain) { // raises acquire_data.ready below
|
||||
when(acquire_data.valid) {
|
||||
abort_cnt := abort_cnt + UFix(1)
|
||||
when(abort_cnt === ~UFix(0, width = log2Up(REFILL_CYCLES))) {
|
||||
abort_state := s_abort_send
|
||||
@ -603,38 +603,38 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren
|
||||
}
|
||||
is(s_abort_send) { // nothing is dequeued for now
|
||||
x_abort.valid := Bool(true)
|
||||
when(x_abort.ready) { // raises x_init.ready
|
||||
when(x_abort.ready) { // raises acquire.ready
|
||||
abort_state := s_idle
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Handle probe request generation
|
||||
val p_req_arb = (new Arbiter(NGLOBAL_XACTS)){(new LogicalNetworkIO){ new Probe }}
|
||||
val probe_arb = (new Arbiter(NGLOBAL_XACTS)){(new LogicalNetworkIO){ new Probe }}
|
||||
for( i <- 0 until NGLOBAL_XACTS ) {
|
||||
val t = trackerList(i).io
|
||||
p_req_arb.io.in(i).bits := t.p_req.bits
|
||||
p_req_arb.io.in(i).valid := t.p_req.valid
|
||||
t.p_req.ready := p_req_arb.io.in(i).ready
|
||||
probe_arb.io.in(i).bits := t.probe.bits
|
||||
probe_arb.io.in(i).valid := t.probe.valid
|
||||
t.probe.ready := probe_arb.io.in(i).ready
|
||||
}
|
||||
io.network.probe <> p_req_arb.io.out
|
||||
io.network.probe <> probe_arb.io.out
|
||||
|
||||
// Handle probe replies, which may or may not have data
|
||||
val p_rep = io.network.release
|
||||
val p_rep_data = io.network.release_data
|
||||
val idx = p_rep.bits.payload.master_xact_id
|
||||
p_rep.ready := trackerList.map(_.io.p_rep.ready).reduce(_||_)
|
||||
p_rep_data.ready := trackerList.map(_.io.p_rep_data.ready).reduce(_||_)
|
||||
p_rep_data_dep_q.io.enq.valid := p_rep.valid && co.messageHasData(p_rep.bits.payload)
|
||||
p_rep_data_dep_q.io.enq.bits.master_xact_id := p_rep.bits.payload.master_xact_id
|
||||
p_rep_data_dep_q.io.deq.ready := trackerList.map(_.io.p_rep_data_dep.ready).reduce(_||_)
|
||||
val release = io.network.release
|
||||
val release_data = io.network.release_data
|
||||
val idx = release.bits.payload.master_xact_id
|
||||
release.ready := trackerList.map(_.io.release.ready).reduce(_||_)
|
||||
release_data.ready := trackerList.map(_.io.release_data.ready).reduce(_||_)
|
||||
release_data_dep_q.io.enq.valid := release.valid && co.messageHasData(release.bits.payload)
|
||||
release_data_dep_q.io.enq.bits.master_xact_id := release.bits.payload.master_xact_id
|
||||
release_data_dep_q.io.deq.ready := trackerList.map(_.io.release_data_dep.ready).reduce(_||_)
|
||||
for( i <- 0 until NGLOBAL_XACTS ) {
|
||||
trackerList(i).io.p_rep_data.valid := p_rep_data.valid
|
||||
trackerList(i).io.p_rep_data.bits := p_rep_data.bits
|
||||
trackerList(i).io.p_rep_data_dep.valid := p_rep_data_dep_q.io.deq.valid
|
||||
trackerList(i).io.p_rep_data_dep.bits := p_rep_data_dep_q.io.deq.bits
|
||||
trackerList(i).io.p_rep.valid := p_rep.valid && (idx === UFix(i))
|
||||
trackerList(i).io.p_rep.bits := p_rep.bits
|
||||
trackerList(i).io.release_data.valid := release_data.valid
|
||||
trackerList(i).io.release_data.bits := release_data.bits
|
||||
trackerList(i).io.release_data_dep.valid := release_data_dep_q.io.deq.valid
|
||||
trackerList(i).io.release_data_dep.bits := release_data_dep_q.io.deq.bits
|
||||
trackerList(i).io.release.valid := release.valid && (idx === UFix(i))
|
||||
trackerList(i).io.release.bits := release.bits
|
||||
}
|
||||
|
||||
// Reply to initial requestor
|
||||
@ -659,11 +659,11 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren
|
||||
}
|
||||
|
||||
// Free finished transactions
|
||||
val finish = io.network.grant_ack
|
||||
val ack = io.network.grant_ack
|
||||
for( i <- 0 until NGLOBAL_XACTS ) {
|
||||
trackerList(i).io.free := finish.valid && (finish.bits.payload.master_xact_id === UFix(i))
|
||||
trackerList(i).io.free := ack.valid && (ack.bits.payload.master_xact_id === UFix(i))
|
||||
}
|
||||
finish.ready := Bool(true)
|
||||
ack.ready := Bool(true)
|
||||
|
||||
// Create an arbiter for the one memory port
|
||||
// We have to arbitrate between the different trackers' memory requests
|
||||
@ -683,20 +683,20 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com
|
||||
val co = conf.co
|
||||
implicit val ln = conf.ln
|
||||
val io = new Bundle {
|
||||
val x_init = (new FIFOIO){(new LogicalNetworkIO) { new Acquire }}.flip
|
||||
val x_init_data = (new FIFOIO){(new LogicalNetworkIO) { new AcquireData }}.flip
|
||||
val p_rep = (new FIFOIO){(new LogicalNetworkIO) { new Release }}.flip
|
||||
val p_rep_data = (new FIFOIO){(new LogicalNetworkIO) { new ReleaseData }}.flip
|
||||
val acquire = (new FIFOIO){(new LogicalNetworkIO) { new Acquire }}.flip
|
||||
val acquire_data = (new FIFOIO){(new LogicalNetworkIO) { new AcquireData }}.flip
|
||||
val release = (new FIFOIO){(new LogicalNetworkIO) { new Release }}.flip
|
||||
val release_data = (new FIFOIO){(new LogicalNetworkIO) { new ReleaseData }}.flip
|
||||
val free = Bool(INPUT)
|
||||
val tile_incoherent = Bits(INPUT, conf.ln.nTiles)
|
||||
val p_rep_data_dep = (new FIFOIO) { new TrackerDependency }.flip
|
||||
val x_init_data_dep = (new FIFOIO) { new TrackerDependency }.flip
|
||||
val release_data_dep = (new FIFOIO) { new TrackerDependency }.flip
|
||||
val acquire_data_dep = (new FIFOIO) { new TrackerDependency }.flip
|
||||
val mem_resp = (new FIFOIO) { new MemResp }.flip
|
||||
|
||||
val mem_req_cmd = (new FIFOIO) { new MemReqCmd }
|
||||
val mem_req_data = (new FIFOIO) { new MemData }
|
||||
val mem_req_lock = Bool(OUTPUT)
|
||||
val p_req = (new FIFOIO) {(new LogicalNetworkIO) { new Probe }}
|
||||
val probe = (new FIFOIO) {(new LogicalNetworkIO) { new Probe }}
|
||||
val grant = (new FIFOIO) {(new LogicalNetworkIO) { new Grant }}
|
||||
val busy = Bool(OUTPUT)
|
||||
val has_conflict = Bool(OUTPUT)
|
||||
@ -708,32 +708,32 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com
|
||||
val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
|
||||
//TODO: Will need id reg for merged release xacts
|
||||
val init_sharer_cnt_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
|
||||
val p_rep_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
|
||||
val p_req_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles))
|
||||
val release_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
|
||||
val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles))
|
||||
val x_needs_read = Reg(resetVal = Bool(false))
|
||||
val x_init_data_needs_write = Reg(resetVal = Bool(false))
|
||||
val p_rep_data_needs_write = Reg(resetVal = Bool(false))
|
||||
val acquire_data_needs_write = Reg(resetVal = Bool(false))
|
||||
val release_data_needs_write = Reg(resetVal = Bool(false))
|
||||
val x_w_mem_cmd_sent = Reg(resetVal = Bool(false))
|
||||
val p_w_mem_cmd_sent = Reg(resetVal = Bool(false))
|
||||
val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
|
||||
val mem_cnt_next = mem_cnt + UFix(1)
|
||||
val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES))
|
||||
val p_req_initial_flags = Bits(width = conf.ln.nTiles)
|
||||
p_req_initial_flags := Bits(0)
|
||||
val probe_initial_flags = Bits(width = conf.ln.nTiles)
|
||||
probe_initial_flags := Bits(0)
|
||||
if (conf.ln.nTiles > 1) {
|
||||
// issue self-probes for uncached read xacts to facilitate I$ coherence
|
||||
// TODO: this is hackish; figure out how to do it more systematically
|
||||
val probe_self = co match {
|
||||
case u: CoherencePolicyWithUncached => u.isUncachedReadTransaction(io.x_init.bits.payload)
|
||||
case u: CoherencePolicyWithUncached => u.isUncachedReadTransaction(io.acquire.bits.payload)
|
||||
case _ => Bool(false)
|
||||
}
|
||||
val myflag = Mux(probe_self, Bits(0), UFixToOH(io.x_init.bits.header.src(log2Up(conf.ln.nTiles)-1,0)))
|
||||
p_req_initial_flags := ~(io.tile_incoherent | myflag)
|
||||
val myflag = Mux(probe_self, Bits(0), UFixToOH(io.acquire.bits.header.src(log2Up(conf.ln.nTiles)-1,0)))
|
||||
probe_initial_flags := ~(io.tile_incoherent | myflag)
|
||||
}
|
||||
val all_grants_require_acks = Bool(true)
|
||||
|
||||
io.busy := state != s_idle
|
||||
io.has_conflict := co.isCoherenceConflict(xact.addr, io.x_init.bits.payload.addr) && (state != s_idle)
|
||||
io.has_conflict := co.isCoherenceConflict(xact.addr, io.acquire.bits.payload.addr) && (state != s_idle)
|
||||
io.mem_req_cmd.valid := Bool(false)
|
||||
io.mem_req_cmd.bits.rw := Bool(false)
|
||||
io.mem_req_cmd.bits.addr := xact.addr
|
||||
@ -741,11 +741,11 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com
|
||||
io.mem_req_data.valid := Bool(false)
|
||||
io.mem_req_data.bits.data := UFix(0)
|
||||
io.mem_req_lock := Bool(false)
|
||||
io.p_req.valid := Bool(false)
|
||||
io.p_req.bits.payload.p_type := co.getProbeType(xact.a_type, UFix(0))
|
||||
io.p_req.bits.payload.master_xact_id := UFix(id)
|
||||
io.p_req.bits.payload.addr := xact.addr
|
||||
io.p_req.bits.header.dst := UFix(0)
|
||||
io.probe.valid := Bool(false)
|
||||
io.probe.bits.payload.p_type := co.getProbeType(xact.a_type, UFix(0))
|
||||
io.probe.bits.payload.master_xact_id := UFix(id)
|
||||
io.probe.bits.payload.addr := xact.addr
|
||||
io.probe.bits.header.dst := UFix(0)
|
||||
io.grant.bits.payload.data := io.mem_resp.bits.data
|
||||
io.grant.bits.payload.g_type := co.getGrantType(xact.a_type, init_sharer_cnt_)
|
||||
io.grant.bits.payload.client_xact_id := xact.client_xact_id
|
||||
@ -753,70 +753,70 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com
|
||||
io.grant.bits.payload.require_ack := all_grants_require_acks
|
||||
io.grant.bits.header.dst := init_client_id_
|
||||
io.grant.valid := (io.mem_resp.valid && (UFix(id) === io.mem_resp.bits.tag))
|
||||
io.x_init.ready := Bool(false)
|
||||
io.x_init_data.ready := Bool(false)
|
||||
io.x_init_data_dep.ready := Bool(false)
|
||||
io.p_rep.ready := Bool(false)
|
||||
io.p_rep_data.ready := Bool(false)
|
||||
io.p_rep_data_dep.ready := Bool(false)
|
||||
io.acquire.ready := Bool(false)
|
||||
io.acquire_data.ready := Bool(false)
|
||||
io.acquire_data_dep.ready := Bool(false)
|
||||
io.release.ready := Bool(false)
|
||||
io.release_data.ready := Bool(false)
|
||||
io.release_data_dep.ready := Bool(false)
|
||||
io.mem_resp.ready := io.grant.ready
|
||||
|
||||
switch (state) {
|
||||
is(s_idle) {
|
||||
when( io.x_init.valid ) {
|
||||
xact := io.x_init.bits.payload
|
||||
init_client_id_ := io.x_init.bits.header.src
|
||||
when( io.acquire.valid ) {
|
||||
xact := io.acquire.bits.payload
|
||||
init_client_id_ := io.acquire.bits.header.src
|
||||
init_sharer_cnt_ := UFix(conf.ln.nTiles) // TODO: Broadcast only
|
||||
x_init_data_needs_write := co.messageHasData(io.x_init.bits.payload)
|
||||
x_needs_read := co.needsMemRead(io.x_init.bits.payload.a_type, UFix(0))
|
||||
p_req_flags := p_req_initial_flags
|
||||
acquire_data_needs_write := co.messageHasData(io.acquire.bits.payload)
|
||||
x_needs_read := co.needsMemRead(io.acquire.bits.payload.a_type, UFix(0))
|
||||
probe_flags := probe_initial_flags
|
||||
mem_cnt := UFix(0)
|
||||
p_w_mem_cmd_sent := Bool(false)
|
||||
x_w_mem_cmd_sent := Bool(false)
|
||||
io.x_init.ready := Bool(true)
|
||||
io.acquire.ready := Bool(true)
|
||||
if(conf.ln.nTiles > 1) {
|
||||
p_rep_count := PopCount(p_req_initial_flags)
|
||||
state := Mux(p_req_initial_flags.orR, s_probe, s_mem)
|
||||
release_count := PopCount(probe_initial_flags)
|
||||
state := Mux(probe_initial_flags.orR, s_probe, s_mem)
|
||||
} else state := s_mem
|
||||
}
|
||||
}
|
||||
is(s_probe) {
|
||||
val curr_p_id = PriorityEncoder(p_req_flags)
|
||||
when(p_req_flags.orR) {
|
||||
io.p_req.valid := Bool(true)
|
||||
io.p_req.bits.header.dst := curr_p_id
|
||||
val curr_p_id = PriorityEncoder(probe_flags)
|
||||
when(probe_flags.orR) {
|
||||
io.probe.valid := Bool(true)
|
||||
io.probe.bits.header.dst := curr_p_id
|
||||
}
|
||||
when(io.p_req.ready) {
|
||||
p_req_flags := p_req_flags & ~(UFixToOH(curr_p_id))
|
||||
when(io.probe.ready) {
|
||||
probe_flags := probe_flags & ~(UFixToOH(curr_p_id))
|
||||
}
|
||||
when(io.p_rep.valid) {
|
||||
io.p_rep.ready := Bool(true)
|
||||
if(conf.ln.nTiles > 1) p_rep_count := p_rep_count - UFix(1)
|
||||
when(p_rep_count === UFix(1)) {
|
||||
when(io.release.valid) {
|
||||
io.release.ready := Bool(true)
|
||||
if(conf.ln.nTiles > 1) release_count := release_count - UFix(1)
|
||||
when(release_count === UFix(1)) {
|
||||
state := s_mem
|
||||
}
|
||||
p_rep_data_needs_write := co.messageHasData(io.p_rep.bits.payload)
|
||||
release_data_needs_write := co.messageHasData(io.release.bits.payload)
|
||||
}
|
||||
}
|
||||
is(s_mem) {
|
||||
when (p_rep_data_needs_write) {
|
||||
when (release_data_needs_write) {
|
||||
doMemReqWrite(io.mem_req_cmd,
|
||||
io.mem_req_data,
|
||||
io.mem_req_lock,
|
||||
io.p_rep_data,
|
||||
p_rep_data_needs_write,
|
||||
io.release_data,
|
||||
release_data_needs_write,
|
||||
p_w_mem_cmd_sent,
|
||||
io.p_rep_data_dep.ready,
|
||||
io.p_rep_data_dep.valid && (io.p_rep_data_dep.bits.master_xact_id === UFix(id)))
|
||||
} . elsewhen(x_init_data_needs_write) {
|
||||
io.release_data_dep.ready,
|
||||
io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(id)))
|
||||
} . elsewhen(acquire_data_needs_write) {
|
||||
doMemReqWrite(io.mem_req_cmd,
|
||||
io.mem_req_data,
|
||||
io.mem_req_lock,
|
||||
io.x_init_data,
|
||||
x_init_data_needs_write,
|
||||
io.acquire_data,
|
||||
acquire_data_needs_write,
|
||||
x_w_mem_cmd_sent,
|
||||
io.x_init_data_dep.ready,
|
||||
io.x_init_data_dep.valid && (io.x_init_data_dep.bits.master_xact_id === UFix(id)))
|
||||
io.acquire_data_dep.ready,
|
||||
io.acquire_data_dep.valid && (io.acquire_data_dep.bits.master_xact_id === UFix(id)))
|
||||
} . elsewhen (x_needs_read) {
|
||||
doMemReqRead(io.mem_req_cmd, x_needs_read)
|
||||
} . otherwise {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user