riscv/rocket-chip
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turn off DRAMSideLLC

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Yunsup Lee 2014-09-11 22:07:44 -07:00
parent 9dfaf5459e
commit b5a64487eb
2 changed files with 5 additions and 3 deletions
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6
src/main/scala/PublicConfigs.scala
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@ -105,7 +105,9 @@ class DefaultConfig extends ChiselConfig {
val data = Mem(Bits(width = 64), 4096, seqRead = true) val data = Mem(Bits(width = 64), 4096, seqRead = true)
Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16,
refill_cycles=refill, tagLeaf=tag, dataLeaf=data)) refill_cycles=refill, tagLeaf=tag, dataLeaf=data))
} else { Module(new DRAMSideLLCNull(16, refill)) } } else {
Module(new DRAMSideLLCNull(8, refill))
}
} }
case BuildCoherenceMaster => (id: Int) => { case BuildCoherenceMaster => (id: Int) => {
if(site[Boolean]("USE_L2_CACHE")) { if(site[Boolean]("USE_L2_CACHE")) {
@ -128,7 +130,7 @@ class DefaultConfig extends ChiselConfig {
} }
case "ENABLE_SHARING" => true case "ENABLE_SHARING" => true
case "ENABLE_CLEAN_EXCLUSIVE" => true case "ENABLE_CLEAN_EXCLUSIVE" => true
case "USE_DRAMSIDE_LLC" => true case "USE_DRAMSIDE_LLC" => false
case "USE_L2_CACHE" => false case "USE_L2_CACHE" => false
} }
} }

2
uncore

@ -1 +1 @@
Subproject commit 5aff088b40d39a8e33549e22c10506589eeab42b Subproject commit b4904e1170928e42733088253c09839a74780df7