riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Reg standardization

Browse Source
This commit is contained in:
Henry Cook
2013-08-13 17:50:02 -07:00
parent 858169917e
commit b570435847
6 changed files with 45 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/tile.scala
View File

@ -19,7 +19,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
if (fastLoadByte) require(fastLoadWord)
}
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(reset = resetSignal) with ClientCoherenceAgent
class Tile(_reset: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = _reset) with ClientCoherenceAgent
{
val memPorts = 2 + confIn.vec
val dcachePortId = 0