riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Reg standardization

Browse Source
This commit is contained in:
Henry Cook
2013-08-13 17:50:02 -07:00
parent 858169917e
commit b570435847
6 changed files with 45 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/ctrl.scala
View File

@ -407,7 +407,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
val wb_reg_div_mul_val = RegReset(Bool(false))
val take_pc = Bool()
val pc_taken = Reg(update = take_pc, reset = Bool(false))
val pc_taken = RegUpdate(take_pc, Bool(false))
val take_pc_wb = Bool()
val ctrl_killd = Bool()
val ctrl_killx = Bool()