riscv/rocket-chip
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Reg standardization

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This commit is contained in:
Henry Cook
2013-08-13 17:50:02 -07:00
parent 858169917e
commit b570435847
6 changed files with 45 additions and 58 deletions
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4
rocket/src/main/scala/core.scala
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@ -42,7 +42,7 @@ class Core(implicit conf: RocketConfiguration) extends Module
} else null
if (conf.vec) {
val vu = Module(new vu(RegUpdate(this.getReset)))
val vu = Module(new vu(RegUpdate(reset)))
val vdtlb = Module(new TLB(8))
ptw += vdtlb.io.ptw
@ -109,7 +109,7 @@ class Core(implicit conf: RocketConfiguration) extends Module
vu.io.xcpt.hold := ctrl.io.vec_iface.hold
// hooking up vector memory interface
dmem(2).req.bits.data := RegEn(StoreGen(vu.io.dmem_req.bits).data, vu.io.dmem_req.valid && isWrite(vu.io.dmem_req.bits.cmd))
dmem(2).req.bits.data := RegEnable(StoreGen(vu.io.dmem_req.bits).data, vu.io.dmem_req.valid && isWrite(vu.io.dmem_req.bits.cmd))
dmem(2).req <> vu.io.dmem_req
dmem(2).resp <> vu.io.dmem_resp