diff --git a/src/main/scala/uncore/tilelink2/Fuzzer.scala b/src/main/scala/uncore/tilelink2/Fuzzer.scala
index deeb936b..30828c61 100644
--- a/src/main/scala/uncore/tilelink2/Fuzzer.scala
+++ b/src/main/scala/uncore/tilelink2/Fuzzer.scala
@@ -218,14 +218,18 @@ class ClockDivider extends BlackBox {
 class TLFuzzRAM extends LazyModule
 {
   val model = LazyModule(new TLRAMModel)
-  val ram  = LazyModule(new TLRAM(AddressSet(0, 0x3ff)))
+  val ram  = LazyModule(new TLRAM(AddressSet(0x800, 0x7ff)))
+  val ram2 = LazyModule(new TLRAM(AddressSet(0, 0x3ff), beatBytes = 16))
   val gpio = LazyModule(new RRTest1(0x400))
   val xbar = LazyModule(new TLXbar)
+  val xbar2= LazyModule(new TLXbar)
   val fuzz = LazyModule(new TLFuzzer(5000))
   val cross = LazyModule(new TLAsyncCrossing)
 
   model.node := fuzz.node
-  xbar.node := TLWidthWidget(TLHintHandler(model.node), 16)
+  xbar2.node := model.node
+  ram2.node := TLFragmenter(xbar2.node, 16, 256)
+  xbar.node := TLWidthWidget(TLHintHandler(xbar2.node), 16)
   cross.node := TLFragmenter(TLBuffer(xbar.node), 4, 256)
   ram.node := cross.node
   gpio.node := TLFragmenter(TLBuffer(xbar.node), 4, 32)
diff --git a/src/main/scala/uncore/tilelink2/Xbar.scala b/src/main/scala/uncore/tilelink2/Xbar.scala
index 9302ea10..4a5bbf40 100644
--- a/src/main/scala/uncore/tilelink2/Xbar.scala
+++ b/src/main/scala/uncore/tilelink2/Xbar.scala
@@ -75,6 +75,23 @@ class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extend
     val inputIdRanges = mapInputIds(node.edgesIn.map(_.client))
     val outputIdRanges = mapOutputIds(node.edgesOut.map(_.manager))
 
+    // Find a good mask for address decoding
+    val port_addrs = node.edgesOut.map(_.manager.managers.map(_.address).flatten)
+    val routingMask = AddressDecoder(port_addrs)
+    val route_addrs = port_addrs.map(_.map(_.widen(~routingMask)).distinct)
+    val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))
+
+    // Print the mapping
+    if (false) {
+      println("Xbar mapping:")
+      route_addrs.foreach { p =>
+        print(" ")
+        p.foreach { a => print(s" ${a}") }
+        println("")
+      }
+      println("--")
+    }
+
     // We need an intermediate size of bundle with the widest possible identifiers
     val wide_bundle = io.in(0).params.union(io.out(0).params)
 
@@ -145,11 +162,15 @@ class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extend
       in(i).e.ready := Mux1C(grantedEIO(i), out.map(_.e.ready))
     }
 
-    val requestAIO = Vec(in.map  { i => Vec(node.edgesOut.map  { o => i.a.valid && o.manager.contains(o.address(i.a.bits)) }) })
-    val requestBOI = Vec(out.map { o => Vec(inputIdRanges.map  { i => o.b.valid && i        .contains(o.b.bits.source)     }) })
-    val requestCIO = Vec(in.map  { i => Vec(node.edgesOut.map  { o => i.c.valid && o.manager.contains(o.address(i.c.bits)) }) })
-    val requestDOI = Vec(out.map { o => Vec(inputIdRanges.map  { i => o.d.valid && i        .contains(o.d.bits.source)     }) })
-    val requestEIO = Vec(in.map  { i => Vec(outputIdRanges.map { o => i.e.valid && o        .contains(i.e.bits.sink)       }) })
+    val addressA = (in zip node.edgesIn) map { case (i, e) => (i.a.valid, e.address(i.a.bits)) }
+    val addressC = (in zip node.edgesIn) map { case (i, e) => (i.c.valid, e.address(i.c.bits)) }
+
+    val requestAIO = Vec(addressA.map { i => Vec(outputPorts.map { o => i._1 && o(i._2) }) })
+    val requestCIO = Vec(addressC.map { i => Vec(outputPorts.map { o => i._1 && o(i._2) }) })
+
+    val requestBOI = Vec(out.map { o => Vec(inputIdRanges.map  { i => o.b.valid && i.contains(o.b.bits.source) }) })
+    val requestDOI = Vec(out.map { o => Vec(inputIdRanges.map  { i => o.d.valid && i.contains(o.d.bits.source) }) })
+    val requestEIO = Vec(in.map  { i => Vec(outputIdRanges.map { o => i.e.valid && o.contains(i.e.bits.sink)   }) })
 
     val beatsA = Vec((in  zip node.edgesIn)  map { case (i, e) => e.numBeats(i.a.bits) })
     val beatsB = Vec((out zip node.edgesOut) map { case (o, e) => e.numBeats(o.b.bits) })