riscv/rocket-chip
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Add FPUParams.fLen option, decoupled from xLen

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This commit is contained in:
Andrew Waterman 2018-02-20 15:43:49 -08:00
parent 5e35015651
commit b487448961
4 changed files with 6 additions and 5 deletions
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4
src/main/scala/rocket/CSR.scala
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@ -333,8 +333,8 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
val isaMaskString = val isaMaskString =
(if (usingMulDiv) "M" else "") + (if (usingMulDiv) "M" else "") +
(if (usingAtomics) "A" else "") + (if (usingAtomics) "A" else "") +
(if (usingFPU) "F" else "") + (if (fLen >= 32) "F" else "") +
(if (usingFPU && xLen > 32) "D" else "") + (if (fLen >= 64) "D" else "") +
(if (usingCompressed) "C" else "") + (if (usingCompressed) "C" else "") +
(if (usingRoCC) "X" else "") (if (usingRoCC) "X" else "")
val isaString = "I" + isaMaskString + val isaString = "I" + isaMaskString +

4
src/main/scala/rocket/RocketCore.scala
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@ -108,8 +108,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
val decode_table = { val decode_table = {
(if (usingMulDiv) new MDecode +: (xLen > 32).option(new M64Decode).toSeq else Nil) ++: (if (usingMulDiv) new MDecode +: (xLen > 32).option(new M64Decode).toSeq else Nil) ++:
(if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++:
(if (usingFPU) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++: (if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++:
(if (usingFPU && xLen > 32) Seq(new DDecode, new D64Decode) else Nil) ++: (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++:
(usingRoCC.option(new RoCCDecode)) ++: (usingRoCC.option(new RoCCDecode)) ++:
((xLen > 32).option(new I64Decode)) ++: ((xLen > 32).option(new I64Decode)) ++:
(usingVM.option(new SDecode)) ++: (usingVM.option(new SDecode)) ++:

2
src/main/scala/tile/Core.scala
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@ -44,7 +44,7 @@ trait CoreParams {
trait HasCoreParameters extends HasTileParameters { trait HasCoreParameters extends HasTileParameters {
val coreParams: CoreParams = tileParams.core val coreParams: CoreParams = tileParams.core
val fLen = xLen // TODO relax this val fLen = coreParams.fpu.map(_.fLen).getOrElse(0)
val usingMulDiv = coreParams.mulDiv.nonEmpty val usingMulDiv = coreParams.mulDiv.nonEmpty
val usingFPU = coreParams.fpu.nonEmpty val usingFPU = coreParams.fpu.nonEmpty

1
src/main/scala/tile/FPU.scala
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@ -14,6 +14,7 @@ import freechips.rocketchip.util.property._
import chisel3.internal.sourceinfo.SourceInfo import chisel3.internal.sourceinfo.SourceInfo
case class FPUParams( case class FPUParams(
fLen: Int = 64,
divSqrt: Boolean = true, divSqrt: Boolean = true,
sfmaLatency: Int = 3, sfmaLatency: Int = 3,
dfmaLatency: Int = 4 dfmaLatency: Int = 4