riscv/rocket-chip
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Add FPUParams.fLen option, decoupled from xLen

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This commit is contained in:
Andrew Waterman
2018-02-20 15:43:49 -08:00
parent 5e35015651
commit b487448961
4 changed files with 6 additions and 5 deletions
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4
src/main/scala/rocket/CSR.scala
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@ -333,8 +333,8 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
val isaMaskString =
(if (usingMulDiv) "M" else "") +
(if (usingAtomics) "A" else "") +
(if (usingFPU) "F" else "") +
(if (usingFPU && xLen > 32) "D" else "") +
(if (fLen >= 32) "F" else "") +
(if (fLen >= 64) "D" else "") +
(if (usingCompressed) "C" else "") +
(if (usingRoCC) "X" else "")
val isaString = "I" + isaMaskString +

4
src/main/scala/rocket/RocketCore.scala
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@ -108,8 +108,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
val decode_table = {
(if (usingMulDiv) new MDecode +: (xLen > 32).option(new M64Decode).toSeq else Nil) ++:
(if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++:
(if (usingFPU) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++:
(if (usingFPU && xLen > 32) Seq(new DDecode, new D64Decode) else Nil) ++:
(if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++:
(if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++:
(usingRoCC.option(new RoCCDecode)) ++:
((xLen > 32).option(new I64Decode)) ++:
(usingVM.option(new SDecode)) ++: