riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2 Arbiter: there is only one winner

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-10-12 18:37:24 -07:00
parent b6e9b0c558
commit b42cfdc9dd
1 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/main/scala/uncore/tilelink2/Arbiter.scala
View File

@ -31,24 +31,24 @@ object TLArbiter
// Arbitrate amongst the requests // Arbitrate amongst the requests
val readys = Vec(policy(valids, latch)) val readys = Vec(policy(valids, latch))
// Which request wins arbitration? // Which request wins arbitration?
val winners = Vec((readys zip valids) map { case (r,v) => r&&v }) val winner = Vec((readys zip valids) map { case (r,v) => r&&v })
// Confirm the policy works properly // Confirm the policy works properly
require (readys.size == valids.size) require (readys.size == valids.size)
// Never two winners // Never two winner
val prefixOR = winners.scanLeft(Bool(false))(_||_).init val prefixOR = winner.scanLeft(Bool(false))(_||_).init
assert((prefixOR zip winners) map { case (p,w) => !p || !w } reduce {_ && _}) assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})
// If there was any request, there is a winner // If there was any request, there is a winner
assert (!valids.reduce(_||_) || winners.reduce(_||_)) assert (!valids.reduce(_||_) || winner.reduce(_||_))
// Track remaining beats // Track remaining beats
val maskedBeats = (winners zip beatsIn) map { case (w,b) => Mux(w, b, UInt(0)) } val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, UInt(0)) }
val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire()) beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire())
// The one-hot source granted access in the previous cycle // The one-hot source granted access in the previous cycle
val state = RegInit(Vec.fill(sources.size)(Bool(false))) val state = RegInit(Vec.fill(sources.size)(Bool(false)))
val muxState = Mux(idle, winners, state) val muxState = Mux(idle, winner, state)
state := muxState state := muxState
if (sources.size > 1) { if (sources.size > 1) {