fix BTB misprediction check for negative addresses
also index BTB with PC, not PC+4
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parent
e9da2cf66a
commit
b3f6f9a5fd
@ -122,7 +122,7 @@ class rocketDpath extends Component
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val if_pc_plus4 = if_reg_pc + UFix(4);
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val ex_pc_plus4 = ex_reg_pc + UFix(4);
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val ex_branch_target = ex_reg_pc + Cat(ex_reg_op2, Bits(0,1)).toUFix
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val ex_branch_target = ex_reg_pc + Cat(ex_reg_op2(VADDR_BITS-1,0), Bits(0,1)).toUFix
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val ex_ea_sign = Mux(ex_alu_adder_out(VADDR_BITS-1), ~ex_alu_adder_out(63,VADDR_BITS) === UFix(0), ex_alu_adder_out(63,VADDR_BITS) != UFix(0))
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val ex_effective_address = Cat(ex_ea_sign, ex_alu_adder_out(VADDR_BITS-1,0)).toUFix
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@ -150,11 +150,11 @@ class rocketDpath extends Component
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Mux(io.ctrl.stallf, if_reg_pc,
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if_next_pc.toUFix);
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btb.io.current_pc4 := if_pc_plus4;
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btb.io.current_pc := if_reg_pc;
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btb.io.hit <> io.ctrl.btb_hit;
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btb.io.wen <> io.ctrl.wen_btb;
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btb.io.clr <> io.ctrl.clr_btb;
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btb.io.correct_pc4 := ex_pc_plus4;
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btb.io.correct_pc := ex_reg_pc;
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io.ctrl.btb_match := id_reg_pc === ex_br_target;
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// instruction decode stage
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@ -8,12 +8,12 @@ import scala.math._;
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class ioDpathBTB extends Bundle()
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{
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val current_pc4 = UFix(VADDR_BITS, INPUT);
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val current_pc = UFix(VADDR_BITS, INPUT);
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val hit = Bool(OUTPUT);
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val target = UFix(VADDR_BITS, OUTPUT);
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val wen = Bool(INPUT);
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val clr = Bool(INPUT);
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val correct_pc4 = UFix(VADDR_BITS, INPUT);
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val correct_pc = UFix(VADDR_BITS, INPUT);
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val correct_target = UFix(VADDR_BITS, INPUT);
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}
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@ -28,15 +28,15 @@ class rocketDpathBTB(entries: Int) extends Component
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val tagmsb = (VADDR_BITS-idxmsb-1)+(VADDR_BITS-idxlsb)-1;
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val taglsb = (VADDR_BITS-idxlsb);
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val vb_array = Mem(entries, io.wen || io.clr, io.correct_pc4(idxmsb,idxlsb), !io.clr, resetVal = Bool(false));
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val tag_target_array = Mem4(entries, io.wen, io.correct_pc4(idxmsb,idxlsb),
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Cat(io.correct_pc4(VADDR_BITS-1,idxmsb+1), io.correct_target(VADDR_BITS-1,idxlsb)))
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val vb_array = Mem(entries, io.wen || io.clr, io.correct_pc(idxmsb,idxlsb), !io.clr, resetVal = Bool(false));
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val tag_target_array = Mem4(entries, io.wen, io.correct_pc(idxmsb,idxlsb),
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Cat(io.correct_pc(VADDR_BITS-1,idxmsb+1), io.correct_target(VADDR_BITS-1,idxlsb)))
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tag_target_array.setReadLatency(0);
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tag_target_array.setTarget('inst);
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val is_val = vb_array(io.current_pc4(idxmsb,idxlsb));
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val tag_target = tag_target_array(io.current_pc4(idxmsb, idxlsb));
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val is_val = vb_array(io.current_pc(idxmsb,idxlsb));
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val tag_target = tag_target_array(io.current_pc(idxmsb, idxlsb));
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io.hit := is_val && (tag_target(tagmsb,taglsb) === io.current_pc4(VADDR_BITS-1, idxmsb+1));
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io.hit := is_val && (tag_target(tagmsb,taglsb) === io.current_pc(VADDR_BITS-1, idxmsb+1));
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io.target := Cat(tag_target(taglsb-1, 0), Bits(0,idxlsb)).toUFix;
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}
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