diff --git a/src/main/scala/devices/tilelink/Clint.scala b/src/main/scala/devices/tilelink/Clint.scala
index 4f6f9726..0f80640b 100644
--- a/src/main/scala/devices/tilelink/Clint.scala
+++ b/src/main/scala/devices/tilelink/Clint.scala
@@ -82,8 +82,8 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
 
     node.regmap(
       0                -> ipi.map(r => RegField(ipiWidth, r)),
-      timecmpOffset(0) -> timecmp.flatMap(r => RegField.bytes(r, timeWidth/8)),
-      timeOffset       -> RegField.bytes(time, timeWidth/8))
+      timecmpOffset(0) -> timecmp.flatMap(RegField.bytes(_)),
+      timeOffset       -> RegField.bytes(time))
   }
 }
 
diff --git a/src/main/scala/regmapper/RegField.scala b/src/main/scala/regmapper/RegField.scala
index 356c1849..3cf0caa8 100644
--- a/src/main/scala/regmapper/RegField.scala
+++ b/src/main/scala/regmapper/RegField.scala
@@ -122,6 +122,12 @@ object RegField
         when (valid) { bytes(i) := data }
         Bool(true)
       }))}}
+
+  def bytes(reg: UInt): Seq[RegField] = {
+    val width = reg.getWidth
+    require (width % 8 == 0, s"RegField.bytes must be called on byte-sized reg, not ${width} bits")
+    bytes(reg, width/8)
+  }
 }
 
 trait HasRegMap