riscv/rocket-chip
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Separate tag ECC and data ECC options (#761)

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This commit is contained in:
Andrew Waterman
2017-05-23 12:51:48 -07:00
committed by Henry Cook
parent 940614625e
commit b2b4c1abcd
5 changed files with 29 additions and 20 deletions
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2
src/main/scala/tile/L1Cache.scala
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@ -15,7 +15,6 @@ trait L1CacheParams {
def nWays: Int
def rowBits: Int
def nTLBEntries: Int
def ecc: Option[Code]
def blockBytes: Int
}
@ -36,7 +35,6 @@ trait HasL1CacheParameters {
def rowBits = cacheParams.rowBits
def rowBytes = rowBits/8
def rowOffBits = log2Up(rowBytes)
def code = cacheParams.ecc.getOrElse(new IdentityCode)
def nTLBEntries = cacheParams.nTLBEntries
def cacheDataBits = p(SharedMemoryTLEdge).bundle.dataBits