riscv/rocket-chip
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Separate tag ECC and data ECC options (#761)

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This commit is contained in:
Andrew Waterman
2017-05-23 12:51:48 -07:00
committed by Henry Cook
parent 940614625e
commit b2b4c1abcd
5 changed files with 29 additions and 20 deletions
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8
src/main/scala/rocket/NBDcache.scala
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@ -669,6 +669,10 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
require(isPow2(nWays)) // TODO: relax this
require(dataScratchpadSize == 0)
// ECC is only supported on the data array
require(cacheParams.tagECC.isInstanceOf[IdentityCode])
val dECC = cacheParams.dataECC
val wb = Module(new WritebackUnit)
val prober = Module(new ProbeUnit)
val mshrs = Module(new MSHRFile)
@ -759,7 +763,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
data.io.write.valid := writeArb.io.out.valid
writeArb.io.out.ready := data.io.write.ready
data.io.write.bits := writeArb.io.out.bits
val wdata_encoded = (0 until rowWords).map(i => code.encode(writeArb.io.out.bits.data(coreDataBits*(i+1)-1,coreDataBits*i)))
val wdata_encoded = (0 until rowWords).map(i => dECC.encode(writeArb.io.out.bits.data(coreDataBits*(i+1)-1,coreDataBits*i)))
data.io.write.bits.data := wdata_encoded.asUInt
// tag read for new requests
@ -822,7 +826,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
s2_data(w) := regs.asUInt
}
val s2_data_muxed = Mux1H(s2_tag_match_way, s2_data)
val s2_data_decoded = (0 until rowWords).map(i => code.decode(s2_data_muxed(encDataBits*(i+1)-1,encDataBits*i)))
val s2_data_decoded = (0 until rowWords).map(i => dECC.decode(s2_data_muxed(encDataBits*(i+1)-1,encDataBits*i)))
val s2_data_corrected = s2_data_decoded.map(_.corrected).asUInt
val s2_data_uncorrected = s2_data_decoded.map(_.uncorrected).asUInt
val s2_word_idx = if(doNarrowRead) UInt(0) else s2_req.addr(log2Up(rowWords*coreDataBytes)-1,log2Up(wordBytes))