From b24c43badb811c4cf4d755905b84584759e43e9a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 9 Mar 2017 16:49:02 -0800 Subject: [PATCH] Don't double-count release traffic in perfctrs --- src/main/scala/rocket/DCache.scala | 4 ++-- src/main/scala/rocket/Frontend.scala | 2 +- src/main/scala/rocket/NBDcache.scala | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index 575f167f..0eab446f 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -505,6 +505,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { } // performance events - io.cpu.acquire := tl_out.a.fire() - io.cpu.release := tl_out.c.fire() + io.cpu.acquire := edge.last(tl_out.a) + io.cpu.release := edge.last(tl_out.c) } diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index b6328f34..0a9875bf 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -155,7 +155,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) io.cpu.resp.bits.btb.bits := s2_btb_resp_bits // performance events - io.cpu.acquire := icache.io.mem(0).a.fire() + io.cpu.acquire := edge.last(icache.io.mem(0).a) } /** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */ diff --git a/src/main/scala/rocket/NBDcache.scala b/src/main/scala/rocket/NBDcache.scala index 5adf56c3..cbe3716f 100644 --- a/src/main/scala/rocket/NBDcache.scala +++ b/src/main/scala/rocket/NBDcache.scala @@ -975,6 +975,6 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule io.cpu.replay_next := (s1_replay && s1_read) || mshrs.io.replay_next // performance events - io.cpu.acquire := tl_out.a.fire() - io.cpu.release := tl_out.c.fire() + io.cpu.acquire := edge.last(tl_out.a) + io.cpu.release := edge.last(tl_out.c) }