From b2351c5fbf8ba84f93f792aad973836fa84136f6 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 6 Jul 2017 11:16:56 -0700 Subject: [PATCH] Use consistent casing --- src/main/scala/rocket/ICache.scala | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index 57368a8c..5cb8c045 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -157,8 +157,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) val accruedRefillError = Reg(Bool()) val refillError = tl_out.d.bits.error || (refill_cnt > 0 && accruedRefillError) when (refill_done) { - val encTag = tECC.encode(Cat(refillError, refill_tag)) - tag_array.write(refill_idx, Vec.fill(nWays)(encTag), Seq.tabulate(nWays)(repl_way === _)) + val enc_tag = tECC.encode(Cat(refillError, refill_tag)) + tag_array.write(refill_idx, Vec.fill(nWays)(enc_tag), Seq.tabulate(nWays)(repl_way === _)) } val vb_array = Reg(init=Bits(0, nSets*nWays)) @@ -174,7 +174,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) } val s1_tag_disparity = Wire(Vec(nWays, Bool())) - val s1_tlError = Wire(Vec(nWays, Bool())) + val s1_tl_error = Wire(Vec(nWays, Bool())) val wordBits = outer.icacheParams.fetchBytes*8 val s1_dout = Wire(Vec(nWays, UInt(width = dECC.width(wordBits)))) @@ -190,11 +190,11 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) lineInScratchpad(scratchpadLine(s1s3_slaveAddr)) && scratchpadWay(s1s3_slaveAddr) === i, addrInScratchpad(io.s1_paddr) && scratchpadWay(io.s1_paddr) === i) val s1_vb = vb_array(Cat(UInt(i), s1_idx)) && !s1_slaveValid - val encTag = tECC.decode(tag_rdata(i)) - val (tlError, tag) = Split(encTag.uncorrected, tagBits) + val enc_tag = tECC.decode(tag_rdata(i)) + val (tl_error, tag) = Split(enc_tag.uncorrected, tagBits) val tagMatch = s1_vb && tag === s1_tag - s1_tag_disparity(i) := s1_vb && encTag.error - s1_tlError(i) := tagMatch && tlError.toBool + s1_tag_disparity(i) := s1_vb && enc_tag.error + s1_tl_error(i) := tagMatch && tl_error.toBool s1_tag_hit(i) := tagMatch || scratchpadHit } assert(!(s1_valid || s1_slaveValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1) @@ -228,7 +228,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) require(dECC.isInstanceOf[uncore.util.IdentityCode]) require(outer.icacheParams.itimAddr.isEmpty) io.resp.bits.data := Mux1H(s1_tag_hit, s1_dout) - io.resp.bits.ae := s1_tlError.asUInt.orR + io.resp.bits.ae := s1_tl_error.asUInt.orR io.resp.valid := s1_valid && s1_hit case 2 => @@ -237,13 +237,13 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) val s2_way_mux = Mux1H(s2_tag_hit, s2_dout) val s2_tag_disparity = RegEnable(s1_tag_disparity, s1_valid || s1_slaveValid).asUInt.orR - val s2_tlError = RegEnable(s1_tlError.asUInt.orR, s1_valid || s1_slaveValid) + val s2_tl_error = RegEnable(s1_tl_error.asUInt.orR, s1_valid || s1_slaveValid) val s2_data_decoded = dECC.decode(s2_way_mux) val s2_disparity = s2_tag_disparity || s2_data_decoded.error when (s2_valid && s2_disparity) { invalidate := true } io.resp.bits.data := s2_data_decoded.uncorrected - io.resp.bits.ae := s2_tlError + io.resp.bits.ae := s2_tl_error io.resp.valid := s2_valid && s2_hit && !s2_disparity tl_in.map { tl =>