riscv/rocket-chip
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Set PRV=M when entering debug mode

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Debug mode mostly behaves like M-mode, so this approach avoids having
to check the debug bit in most permission checks.
This commit is contained in:
Andrew Waterman
2017-03-14 14:37:09 -07:00
parent cf168e419b
commit b1b405404d
2 changed files with 8 additions and 8 deletions
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src/main/scala/rocket/TLB.scala
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@ -63,7 +63,7 @@ class TLB(entries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreMod
val do_mprv = io.ptw.status.mprv && !io.req.bits.instruction
val priv = Mux(do_mprv, io.ptw.status.mpp, io.ptw.status.prv)
val priv_s = priv === PRV.S
val priv_uses_vm = priv <= PRV.S && !io.ptw.status.debug
val priv_uses_vm = priv <= PRV.S
val vm_enabled = Bool(usingVM) && io.ptw.ptbr.mode(io.ptw.ptbr.mode.getWidth-1) && priv_uses_vm && !io.req.bits.passthrough
// share a single physical memory attribute checker (unshare if critical path)