diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index 1486c3d4..bcdea1e6 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -388,6 +388,10 @@ class rocketDpath extends Component
     vec.io.pcrw.en := io.ctrl.wen_pcr
     vec.io.pcrw.data := wb_reg_wdata
 
+    pcr.io.vec_appvl := vec.io.appvl
+    pcr.io.vec_nxregs := vec.io.nxregs
+    pcr.io.vec_nfregs := vec.io.nfregs
+
     wb_wdata :=
       Mux(vec.io.wen, Cat(Bits(0,52), vec.io.appvl),
       Mux(wb_src_dmem, io.dmem.resp_data_subword,
@@ -395,6 +399,10 @@ class rocketDpath extends Component
   }
   else
   {
+    pcr.io.vec_appvl := UFix(0)
+    pcr.io.vec_nxregs := UFix(0)
+    pcr.io.vec_nfregs := UFix(0)
+
     wb_wdata :=
       Mux(wb_src_dmem, io.dmem.resp_data_subword,
           wb_reg_wdata)
diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala
index 2748048c..b5986bfe 100644
--- a/rocket/src/main/scala/dpath_util.scala
+++ b/rocket/src/main/scala/dpath_util.scala
@@ -80,6 +80,9 @@ class ioDpathPCR extends Bundle()
   val vecbank   = Bits(8, OUTPUT)
   val vecbankcnt = UFix(4, OUTPUT)
   val vechold = Bool(OUTPUT)
+  val vec_appvl = UFix(12, INPUT)
+  val vec_nxregs = UFix(6, INPUT)
+  val vec_nfregs = UFix(6, INPUT)
 }
 
 class rocketDpathPCR extends Component
@@ -229,6 +232,7 @@ class rocketDpathPCR extends Component
       is (PCR_K1)       { rdata := reg_k1; }
       is (PCR_PTBR)     { rdata := Cat(Bits(0,64-PADDR_BITS), reg_ptbr); }
       is (PCR_VECBANK)  { rdata := Cat(Bits(0, 56), reg_vecbank) }
+      is (PCR_VECCFG)   { rdata := Cat(Bits(0, 40), io.vec_nfregs, io.vec_nxregs, io.vec_appvl) }
     }
   }
 }
diff --git a/rocket/src/main/scala/dpath_vec.scala b/rocket/src/main/scala/dpath_vec.scala
index d557341a..95653b98 100644
--- a/rocket/src/main/scala/dpath_vec.scala
+++ b/rocket/src/main/scala/dpath_vec.scala
@@ -34,6 +34,8 @@ class ioDpathVec extends Bundle
   val pcrw = new ioWritePort()
   val wen = Bool(OUTPUT)
   val appvl = UFix(12, OUTPUT)
+  val nxregs = UFix(6, OUTPUT)
+  val nfregs = UFix(6, OUTPUT)
 }
 
 class rocketDpathVec extends Component
@@ -134,7 +136,10 @@ class rocketDpathVec extends Component
   }
 
   io.wen := io.valid && io.ctrl.wen
-  io.appvl := appvl
+  io.appvl := Mux(io.ctrl.fn === VEC_VL || io.ctrl.fn === VEC_CFGVL, appvl, reg_appvl)
+  io.nxregs := reg_nxregs
+  io.nfregs := reg_nfregs
+
   val appvlm1 = appvl - UFix(1)
 
   io.iface.vcmdq_bits :=
@@ -148,7 +153,7 @@ class rocketDpathVec extends Component
         Bits(0,20))))))))
 
   io.iface.vximm1q_bits :=
-    Mux(io.ctrl.sel_vimm === VIMM_VLEN, Cat(Bits(0,29), io.vecbankcnt, io.vecbank, nfregs, nxregs, appvlm1(10,0)),
+    Mux(io.ctrl.sel_vimm === VIMM_VLEN, Cat(Bits(0,29), io.vecbankcnt, io.vecbank, nfregs(5,0), nxregs(5,0), appvlm1(10,0)),
         io.wdata) // VIMM_ALU
 
   io.iface.vximm2q_bits :=