diff --git a/scripts/vlsi_mem_gen b/scripts/vlsi_mem_gen
index 314ffb9a..d5ec2b17 100755
--- a/scripts/vlsi_mem_gen
+++ b/scripts/vlsi_mem_gen
@@ -89,19 +89,29 @@ def gen_mem(name, width, depth, mask_gran, mask_seg, ports):
   masked = len(maskedports)>0
   tup = (depth, width, nr, nw, nrw, masked)
 
-  for idx in range(nr):
-    prefix = 'R%d_' % idx
+  def emit_read(idx, rw):
+    prefix = ('RW%d_' if rw else 'R%d_') % idx
+    data = ('%srdata' if rw else '%sdata') % prefix
+    en = ('%sen && !%swmode' % (prefix, prefix)) if rw else ('%sen' % prefix)
+    decl.append('reg reg_%sren;' % prefix)
     decl.append('reg [%d:0] reg_%saddr;' % (addr_width-1, prefix))
     sequential.append('always @(posedge %sclk)' % prefix)
-    sequential.append('  if (%sen) reg_%saddr <= %saddr;' % (prefix, prefix, prefix))
-    combinational.append('assign %sdata = ram[reg_%saddr];' % (prefix, prefix))
+    sequential.append('  reg_%sren <= %s;' % (prefix, en))
+    sequential.append('always @(posedge %sclk)' % prefix)
+    sequential.append('  if (%s) reg_%saddr <= %saddr;' % (en, prefix, prefix))
+    combinational.append('`ifdef RANDOMIZE_GARBAGE_ASSIGN')
+    combinational.append('reg [%d:0] %srandom;' % (((width-1)//32+1)*32-1, prefix))
+    combinational.append('always @(posedge %sclk) %srandom <= {%s};' % (prefix, prefix, ', '.join(['$random'] * ((width-1)//32+1))))
+    combinational.append('assign %s = reg_%sren ? ram[reg_%saddr] : %srandom[%d:0];' % (data, prefix, prefix, prefix, width-1))
+    combinational.append('`else')
+    combinational.append('assign %s = ram[reg_%saddr];' % (data, prefix))
+    combinational.append('`endif')
+
+  for idx in range(nr):
+    emit_read(idx, False)
 
   for idx in range(nrw):
-    prefix = 'RW%d_' % idx
-    decl.append('reg [%d:0] reg_%saddr;' % (addr_width-1, prefix))
-    sequential.append('always @(posedge %sclk)' % prefix)
-    sequential.append('  if (%sen && !%swmode) reg_%saddr <= %saddr;' % (prefix, prefix, prefix, prefix))
-    combinational.append('assign %srdata = ram[reg_%saddr];' % (prefix, prefix))
+    emit_read(idx, True)
 
   for idx in range(len(latchports)):
     prefix = 'W%d_' % idx
@@ -123,13 +133,13 @@ def gen_mem(name, width, depth, mask_gran, mask_seg, ports):
   decl.append('  initial begin')
   decl.append('    #0.002 begin end')
   decl.append('    for (initvar = 0; initvar < %d; initvar = initvar+1)' % depth)
-  decl.append('      ram[initvar] = {%d {$random}};' % ((width-1)/32+1))
+  decl.append('      ram[initvar] = {%d {$random}};' % ((width-1)//32+1))
   for idx in range(nr):
     prefix = 'R%d_' % idx
-    decl.append('    reg_%saddr = {%d {$random}};' % (prefix, ((addr_width-1)/32+1)))
+    decl.append('    reg_%saddr = {%d {$random}};' % (prefix, ((addr_width-1)//32+1)))
   for idx in range(nrw):
     prefix = 'RW%d_' % idx
-    decl.append('    reg_%saddr = {%d {$random}};' % (prefix, ((addr_width-1)/32+1)))
+    decl.append('    reg_%saddr = {%d {$random}};' % (prefix, ((addr_width-1)//32+1)))
   decl.append('  end')
   decl.append('`endif')