riscv/rocket-chip
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make outer cache type choice a top-level const

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Henry Cook 2014-05-06 13:11:41 -07:00
parent d2a3b1dc20
commit b0ccb88982
1 changed files with 2 additions and 1 deletions
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src/main/scala/RocketChip.scala
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@ -11,6 +11,7 @@ object DesignSpaceConstants {
val HTIF_WIDTH = 16 val HTIF_WIDTH = 16
val ENABLE_SHARING = true val ENABLE_SHARING = true
val ENABLE_CLEAN_EXCLUSIVE = true val ENABLE_CLEAN_EXCLUSIVE = true
val USE_DRAMSIDE_LLC = true
val HAS_FPU = true val HAS_FPU = true
val NL2_REL_XACTS = 1 val NL2_REL_XACTS = 1
val NL2_ACQ_XACTS = 7 val NL2_ACQ_XACTS = 7
@ -220,7 +221,7 @@ class Top extends Module {
atomicOpBits = ATOMIC_OP_BITS) atomicOpBits = ATOMIC_OP_BITS)
implicit val l2 = L2CacheConfig(512, 8, 1, 1, NL2_REL_XACTS, NL2_ACQ_XACTS, tl, as) implicit val l2 = L2CacheConfig(512, 8, 1, 1, NL2_REL_XACTS, NL2_ACQ_XACTS, tl, as)
implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, MEM_DATA_BEATS) implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, MEM_DATA_BEATS)
implicit val uc = UncoreConfiguration(l2, tl, mif, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS, useDRAMSideLLC = true) implicit val uc = UncoreConfiguration(l2, tl, mif, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS, useDRAMSideLLC = USE_DRAMSIDE_LLC)
val ic = ICacheConfig(sets = 128, assoc = 2, ntlb = 8, tl = tl, as = as, btb = BTBConfig(as, 64, 2)) val ic = ICacheConfig(sets = 128, assoc = 2, ntlb = 8, tl = tl, as = as, btb = BTBConfig(as, 64, 2))
val dc = DCacheConfig(sets = 128, ways = 4, val dc = DCacheConfig(sets = 128, ways = 4,