riscv/rocket-chip
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fix a few Chisel3 compat issues

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This commit is contained in:
Howard Mao 2015-11-20 13:33:15 -08:00
parent 0f092b9b59
commit b0a06a77db
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/nbdcache.scala
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@ -1079,7 +1079,7 @@ class SimpleHellaCacheIF(implicit p: Parameters) extends Module
val cache = new HellaCacheIO
}
val replaying_cmb = Bool()
val replaying_cmb = Wire(Bool())
val replaying = Reg(next = replaying_cmb, init = Bool(false))
replaying_cmb := replaying
@ -1099,10 +1099,10 @@ class SimpleHellaCacheIF(implicit p: Parameters) extends Module
val s1_req_fire = Reg(next=s0_req_fire)
val s2_req_fire = Reg(next=s1_req_fire)
io.cache.req <> req_arb.io.out
io.cache.req.bits.kill := s2_nack
io.cache.req.bits.phys := Bool(true)
io.cache.req.bits.data := RegEnable(req_arb.io.out.bits.data, s0_req_fire)
io.cache.req <> req_arb.io.out
/* replay queues:
replayq1 holds the older request.