tilelink2: add a Fragmenter adapter
God that was a pain in the ass!
This commit is contained in:
Wesley W. Terpstra
parent
ecc3c2a4b2
commit
b004d54d71
255
uncore/src/main/scala/tilelink2/Fragmenter.scala
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255
uncore/src/main/scala/tilelink2/Fragmenter.scala
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import scala.math.{min,max}
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// minSize: minimum size of transfers supported by all outward managers
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// maxSize: maximum size of transfers supported after the Fragmenter is applied
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// alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager)
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// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
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// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
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// Fragmenter breaks: Acquire (and thus cuts BCE channels)
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class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) extends LazyModule
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{
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require (isPow2 (maxSize))
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require (isPow2 (minSize))
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require (minSize < maxSize)
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require (maxSize <= TransferSizes.maxAllowed)
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val fragmentBits = log2Ceil(maxSize / minSize)
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def expandTransfer(x: TransferSizes) = if (!x) x else {
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require (x.max >= minSize) // validate that we can apply the fragmenter correctly
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TransferSizes(x.min, maxSize)
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}
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def shrinkTransfer(x: TransferSizes) =
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if (!alwaysMin) x else
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if (x.min <= minSize) TransferSizes(x.min, minSize) else
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TransferSizes.none
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def mapManager(m: TLManagerParameters) = m.copy(
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supportsAcquire = TransferSizes.none, // this adapter breaks acquires
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supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
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supportsLogical = expandTransfer(m.supportsLogical),
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supportsGet = expandTransfer(m.supportsGet),
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supportsPutFull = expandTransfer(m.supportsPutFull),
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supportsPutPartial = expandTransfer(m.supportsPutPartial))
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def mapClient(c: TLClientParameters) = c.copy(
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sourceId = IdRange(c.sourceId.start << fragmentBits, c.sourceId.end << fragmentBits),
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// since we break Acquires, none of these work either:
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supportsProbe = TransferSizes.none,
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supportsArithmetic = TransferSizes.none,
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supportsLogical = TransferSizes.none,
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supportsGet = TransferSizes.none,
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supportsPutFull = TransferSizes.none,
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supportsPutPartial = TransferSizes.none,
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supportsHint = false)
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val node = TLAdapterNode(
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clientFn = { case Seq(c) => c.copy(clients = c.clients.map(mapClient)) },
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managerFn = { case Seq(m) => m.copy(managers = m.managers.map(mapManager)) })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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// All managers must share a common FIFO domain (responses might end up interleaved)
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val manager = node.edgesOut(0).manager
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val managers = manager.managers
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val beatBytes = manager.beatBytes
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val fifoId = managers(0).fifoId
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require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _))
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// We don't support fragmenting to sub-beat accesses
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require (minSize >= beatBytes)
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/* The Fragmenter is a bit tricky, because there are 5 sizes in play:
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* max size -- the maximum transfer size possible
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* orig size -- the original pre-fragmenter size
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* frag size -- the modified post-fragmenter size
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* min size -- the threshold below which frag=orig
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* beat size -- the amount transfered on any given beat
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*
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* The relationships are as follows:
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* max >= orig >= frag
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* max > min >= beat
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* It IS possible that orig <= min (then frag=orig; ie: no fragmentation)
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*
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* The fragment# (sent via TL.source) is measured in multiples of min size.
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* Meanwhile, to track the progress, counters measure in multiples of beat size.
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*
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* Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16.
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*
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* in.A out.A (frag#) out.D (frag#) in.D gen# ack#
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* get64 get16 6 ackD16 6 ackD64 12 15
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* ackD16 6 ackD64 14
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* ackD16 6 ackD64 13
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* ackD16 6 ackD64 12
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* get16 4 ackD16 4 ackD64 8 11
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* ackD16 4 ackD64 10
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* ackD16 4 ackD64 9
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* ackD16 4 ackD64 8
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* get16 2 ackD16 2 ackD64 4 7
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* ackD16 2 ackD64 6
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* ackD16 2 ackD64 5
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* ackD16 2 ackD64 4
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* get16 0 ackD16 0 ackD64 0 3
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* ackD16 0 ackD64 2
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* ackD16 0 ackD64 1
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* ackD16 0 ackD64 0
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*
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* get8 get8 0 ackD8 0 ackD8 0 1
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* ackD8 0 ackD8 0
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*
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* get4 get4 0 ackD4 0 ackD4 0 0
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* get1 get1 0 ackD1 0 ackD1 0 0
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*
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* put64 put16 6 15
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* put64 put16 6 14
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* put64 put16 6 13
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* put64 put16 6 ack16 6 12 12
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* put64 put16 4 11
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* put64 put16 4 10
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* put64 put16 4 9
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* put64 put16 4 ack16 4 8 8
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* put64 put16 2 7
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* put64 put16 2 6
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* put64 put16 2 5
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* put64 put16 2 ack16 2 4 4
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* put64 put16 0 3
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* put64 put16 0 2
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* put64 put16 0 1
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* put64 put16 0 ack16 0 ack64 0 0
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*
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* put8 put8 0 1
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* put8 put8 0 ack8 0 ack8 0 0
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*
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* put4 put4 0 ack4 0 ack4 0 0
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* put1 put1 0 ack1 0 ack1 0 0
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*/
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val in = io.in(0)
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val out = io.out(0)
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// Do there exist A messages with Data? (we don't count Arithmetic, because it is never fragmented)
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val aDataYes = manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
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// Do there exist A messages without Data?
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val aDataNo = manager.anySupportGet || manager.anySupportHint
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// Do there eixst D messages with Data?
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val dDataYes = manager.anySupportGet || manager.anySupportLogical
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// Do there exist D messages without Data?
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val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint
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val counterBits = log2Up(maxSize/beatBytes)
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val maxDownSize = if (alwaysMin) minSize else manager.maxTransfer
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def OH1ToUInt(x: UInt) = OHToUInt((x << 1 | UInt(1)) ^ x)
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def UIntToOH1(x: UInt, width: Int) = (UInt((1 << width) - 1) << x)(width*2-1, width)
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// First, handle the return path
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val acknum = RegInit(UInt(0, width = counterBits))
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val dOrig = Reg(UInt())
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val dFragnum = out.d.bits.source(fragmentBits-1, 0)
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val dFirst = acknum === UInt(0)
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val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1)
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val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Ceil(maxDownSize))
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// It is important to optimize this to a constant if we know certain operaitons
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// will never exist. This allows synthesis to eliminate the Muxes.
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val dHasData = if (!dDataYes) Bool(false) else if (!dDataNo) Bool(true) else out.d.bits.hasData()
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// calculate new acknum
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val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes)
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val acknum_size = dsizeOH1 >> log2Ceil(beatBytes)
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assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))
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val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, UInt(0))
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val ack_decrement = Mux(dHasData, UInt(1), dsizeOH >> log2Ceil(beatBytes))
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// calculate the original size
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val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1)
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when (out.d.fire()) {
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acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement)
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when (dFirst) { dOrig := dFirst_size }
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}
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// Swallow up non-data ack fragments
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val drop = (out.d.bits.opcode === TLMessages.AccessAck) && (dFragnum =/= UInt(0))
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out.d.ready := in.d.ready || drop
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in.d.valid := out.d.valid && drop
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in.d.bits := out.d.bits // pass most stuff unchanged
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in.d.bits.source := out.d.bits.source >> fragmentBits
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in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)
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// What maximum transfer sizes do downstream devices support?
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val maxArithmetics = managers.map(_.supportsArithmetic.max)
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val maxLogicals = managers.map(_.supportsLogical.max)
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val maxGets = managers.map(_.supportsGet.max)
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val maxPutFulls = managers.map(_.supportsPutFull.max)
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val maxPutPartials = managers.map(_.supportsPutPartial.max)
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val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0)
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// We assume that the request is valid => size 0 is impossible
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val lgMinSize = UInt(log2Ceil(minSize))
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val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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// If this is infront of a single manager, these become constants
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val find = manager.find(in.a.bits.address)
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val maxLgArithmetic = Mux1H(find, maxLgArithmetics)
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val maxLgLogical = Mux1H(find, maxLgLogicals)
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val maxLgGet = Mux1H(find, maxLgGets)
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val maxLgPutFull = Mux1H(find, maxLgPutFulls)
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val maxLgPutPartial = Mux1H(find, maxLgPutPartials)
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val maxLgHint = Mux1H(find, maxLgHints)
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val limit = if (alwaysMin) lgMinSize else
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MuxLookup(in.a.bits.opcode, lgMinSize, Array(
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TLMessages.PutFullData -> maxLgPutFull,
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TLMessages.PutPartialData -> maxLgPutPartial,
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TLMessages.ArithmeticData -> maxLgArithmetic,
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TLMessages.LogicalData -> maxLgLogical,
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TLMessages.Get -> maxLgGet,
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TLMessages.Hint -> maxLgHint))
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val aOrig = in.a.bits.size
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val aFrag = Mux(aOrig > limit, limit, aOrig)
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val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
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val aFragOH1 = UIntToOH1(aFrag, log2Ceil(maxDownSize))
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// Statically optimize the case where hasData is a constant
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val aHasData = if (!aDataYes) Bool(false) else if (!aDataNo) Bool(true) else out.a.bits.hasData()
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val aMask = Mux(aHasData, UInt(0), aFragOH1)
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val gennum = RegInit(UInt(0, width = counterBits))
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val aFirst = gennum === UInt(0)
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val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - UInt(1))
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val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe
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val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize)))
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when (out.d.fire()) { gennum := new_gennum }
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val delay = !aHasData && aFragnum =/= UInt(0)
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out.a.valid := in.a.valid
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in.a.ready := out.a.ready && !delay
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out.a.bits := in.a.bits
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out.a.bits.source := Cat(in.a.bits.source, aFragnum)
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out.a.bits.size := aFrag
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}
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}
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object TLFragmenter
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{
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// applied to the TL source node; connect (TLFragmenter(x.node, 256, 4) -> y.node)
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def apply(x: TLBaseNode, minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(implicit lazyModule: LazyModule): TLBaseNode = {
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val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin))
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lazyModule.connect(x -> fragmenter.node)
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fragmenter.node
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}
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}
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