Integrate L1 BusErrorUnit

2017-09-15 18:49:40 -07:00
parent dbf599f6a1
commit afad25fceb
6 changed files with 39 additions and 5 deletions
--- a/src/main/scala/coreplex/RocketCoreplex.scala
+++ b/src/main/scala/coreplex/RocketCoreplex.scala
@ -84,6 +84,8 @@ trait HasRocketTiles extends HasSystemBus
    lip.foreach { coreIntXbar.intnode := _ }                // lip
    wrapper.coreIntNode   := coreIntXbar.intnode

+    wrapper.intOutputNode.foreach { plic.intnode := _ }
+
    wrapper
  }
 }