don't use ROM for partial writemask regression
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@ -215,16 +215,13 @@ class WriteMaskedPutBlockRegression(implicit p: Parameters) extends Regression()
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val (put_beat, put_block_done) = Counter(
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val (put_beat, put_block_done) = Counter(
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io.mem.acquire.fire() && acq.hasData(), tlDataBeats)
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io.mem.acquire.fire() && acq.hasData(), tlDataBeats)
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val put_data = UInt(0x30010040, tlDataBits) + (put_beat << UInt(2))
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val data_beats = Vec.tabulate(tlDataBeats) {
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i => UInt(0x3001040 + i * 4, tlDataBits)
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}
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val put_acq = PutBlock(
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val put_acq = PutBlock(
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client_xact_id = UInt(0),
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client_xact_id = UInt(0),
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addr_block = UInt(7),
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addr_block = UInt(7),
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addr_beat = put_beat,
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addr_beat = put_beat,
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data = Mux(put_beat(0) === stage, data_beats(put_beat), UInt(0)),
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data = Mux(put_beat(0) === stage, put_data, UInt(0)),
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wmask = Mux(put_beat(0) === stage, Acquire.fullWriteMask, Bits(0)))
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wmask = Mux(put_beat(0) === stage, Acquire.fullWriteMask, Bits(0)))
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val get_acq = GetBlock(
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val get_acq = GetBlock(
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@ -237,6 +234,7 @@ class WriteMaskedPutBlockRegression(implicit p: Parameters) extends Regression()
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val (get_cnt, get_done) = Counter(
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val (get_cnt, get_done) = Counter(
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io.mem.grant.fire() && gnt.hasData(), tlDataBeats)
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io.mem.grant.fire() && gnt.hasData(), tlDataBeats)
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val get_data = UInt(0x30010040, tlDataBits) + (get_cnt << UInt(2))
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val (stall_cnt, stall_done) = Counter(state === s_stall, 16)
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val (stall_cnt, stall_done) = Counter(state === s_stall, 16)
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@ -262,7 +260,7 @@ class WriteMaskedPutBlockRegression(implicit p: Parameters) extends Regression()
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assert(!io.mem.grant.valid ||
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assert(!io.mem.grant.valid ||
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!io.mem.grant.bits.hasData() ||
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!io.mem.grant.bits.hasData() ||
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stage === UInt(0) ||
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stage === UInt(0) ||
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io.mem.grant.bits.data === data_beats(get_cnt),
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io.mem.grant.bits.data === get_data,
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"WriteMaskedPutBlockRegression: data does not match")
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"WriteMaskedPutBlockRegression: data does not match")
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}
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}
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