regmapper: add byte-sized RegField helper function (#854)
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@ -77,6 +77,7 @@ case class RegField(width: Int, read: RegReadFn, write: RegWriteFn, name: String
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{
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{
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require (width > 0, s"RegField width must be > 0, not $width")
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require (width > 0, s"RegField width must be > 0, not $width")
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def pipelined = !read.combinational || !write.combinational
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def pipelined = !read.combinational || !write.combinational
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def readOnly = this.copy(write = ())
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}
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}
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object RegField
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object RegField
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@ -105,6 +106,22 @@ object RegField
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bb.d := data
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bb.d := data
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Bool(true)
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Bool(true)
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}))
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}))
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// Create byte-sized read-write RegFields out of a large UInt register.
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// It is updated when any of the bytes are written. Because the RegFields
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// are all byte-sized, this is also suitable when a register is larger
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// than the intended bus width of the device (atomic updates are impossible).
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def bytes(reg: UInt, numBytes: Int): Seq[RegField] = {
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val pad = reg | UInt(0, width = 8*numBytes)
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val bytes = Wire(init = Vec.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) })
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val valids = Wire(init = Vec.fill(numBytes) { Bool(false) })
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when (valids.reduce(_ || _)) { reg := bytes.asUInt }
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bytes.zipWithIndex.map { case (b, i) => RegField(8, b,
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RegWriteFn((valid, data) => {
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valids(i) := valid
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when (valid) { bytes(i) := data }
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Bool(true)
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}))}}
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}
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}
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trait HasRegMap
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trait HasRegMap
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