riscv/rocket-chip
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use the uncached port instead of the cached port

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This commit is contained in:
Howard Mao 2015-10-26 23:09:36 -07:00
parent b22088d934
commit aeb9c86459
2 changed files with 15 additions and 22 deletions
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21
groundtest/src/main/scala/generator.scala
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@ -6,7 +6,6 @@ import junctions._
import scala.util.Random
import cde.{Parameters, Field}
case object BuildGenerator extends Field[(Int, Random, Parameters) => TileLinkGenerator]
case object NGeneratorsPerTile extends Field[Int]
case object NGeneratorTiles extends Field[Int]
@ -17,22 +16,17 @@ trait HasGeneratorParams {
val nGens = nGensPerTile * nGenTiles
}
abstract class TileLinkGenerator(rnd: Random)
class UncachedTileLinkGenerator(id: Int)
(implicit p: Parameters) extends TLModule()(p) with HasGeneratorParams {
val io = new Bundle {
val tl = new ClientTileLinkIO
val finished = Bool(OUTPUT)
}
}
class UncachedTileLinkGenerator(id: Int, rnd: Random)
(implicit p: Parameters) extends TileLinkGenerator(rnd)(p) {
private val tlBlockOffset = tlBeatAddrBits + tlByteAddrBits
private val maxAddress = (p(MMIOBase) >> tlBlockOffset).toInt
private val totalRequests = maxAddress / nGens
def rndDataBeat(): UInt = { UInt(BigInt(tlDataBits, rnd), tlDataBits) }
val io = new Bundle {
val tl = new ClientUncachedTileLinkIO
val finished = Bool(OUTPUT)
}
val (s_start :: s_put :: s_get :: s_finished :: Nil) = Enum(Bits(), 4)
val state = Reg(init = s_start)
@ -88,9 +82,4 @@ class UncachedTileLinkGenerator(id: Int, rnd: Random)
assert(!io.tl.grant.valid || state != s_get ||
io.tl.grant.bits.data === get_data,
"Get received incorrect data")
io.tl.release.valid := Bool(false)
io.tl.probe.ready := Bool(false)
assert(!io.tl.probe.valid, "Uncached generator cannot accept probes")
}

16
groundtest/src/main/scala/tile.scala
View File

@ -6,23 +6,27 @@ import uncore._
import scala.util.Random
import cde.Parameters
class GeneratorTile(id: Int, rnd: Random, resetSignal: Bool)
class GeneratorTile(id: Int, resetSignal: Bool)
(implicit val p: Parameters) extends Tile(resetSignal)(p)
with HasGeneratorParams {
val gen_finished = Wire(Vec(nGensPerTile, Bool()))
val arb = Module(new ClientTileLinkIOArbiter(nGensPerTile))
val arb = Module(new ClientUncachedTileLinkIOArbiter(nGensPerTile))
for (i <- 0 until nGensPerTile) {
val genid = id * nGensPerTile + i
val generator = p(BuildGenerator)(genid, rnd, p)
val generator = Module(new UncachedTileLinkGenerator(genid))
arb.io.in(i) <> generator.io.tl
gen_finished(i) := generator.io.finished
}
io.cached(0) <> arb.io.out
io.uncached(0).acquire.valid := Bool(false)
io.uncached(0).grant.ready := Bool(false)
io.uncached(0) <> arb.io.out
io.cached(0).acquire.valid := Bool(false)
io.cached(0).grant.ready := Bool(false)
io.cached(0).probe.ready := Bool(false)
io.cached(0).release.valid := Bool(false)
assert(!io.cached(0).probe.valid, "Shouldn't be receiving probes")
val all_done = gen_finished.reduce(_ && _)