From ae98af707731e771e2a73a0de5583dcb87dbbc7c Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 12 Jan 2016 16:27:14 -0800 Subject: [PATCH] don't mix SInt/UInt --- rocket/src/main/scala/fpu.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index 7da59549..35b36a5e 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -305,12 +305,12 @@ class IntToFP(val latency: Int) extends Module Mux(in.bits.typ(0), in.bits.in1(31,0).zext, in.bits.in1(31,0).toSInt)) val l2s = Module(new hardfloat.INToRecFN(64, 8, 24)) l2s.io.signedIn := ~in.bits.typ(0) - l2s.io.in := longValue + l2s.io.in := longValue.toUInt l2s.io.roundingMode := in.bits.rm val l2d = Module(new hardfloat.INToRecFN(64, 11, 53)) l2d.io.signedIn := ~in.bits.typ(0) - l2d.io.in := longValue + l2d.io.in := longValue.toUInt l2d.io.roundingMode := in.bits.rm when (in.bits.cmd === FCMD_CVT_FI) {