more amo fixes, added more options to testharness to control debug messages
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82a636ff55
commit
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@ -570,8 +570,9 @@ class rocketCtrl extends Component
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io.dpath.stalld
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io.dpath.stalld
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);
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);
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// check for loads in execute and mem stages to detect load/use hazards
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// check for loads and amos in execute and mem stages to detect load/use hazards
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val ex_mem_cmd_load = ex_reg_mem_val && (ex_reg_mem_cmd === M_XRD);
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val ex_mem_cmd_load =
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ex_reg_mem_val && ((ex_reg_mem_cmd === M_XRD) || ex_reg_mem_cmd(3).toBool);
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val lu_stall_ex =
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val lu_stall_ex =
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ex_mem_cmd_load &&
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ex_mem_cmd_load &&
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@ -643,7 +644,7 @@ class rocketCtrl extends Component
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io.dpath.killx := kill_ex.toBool;
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io.dpath.killx := kill_ex.toBool;
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io.dpath.killm := kill_mem.toBool;
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io.dpath.killm := kill_mem.toBool;
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io.dpath.mem_load := mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD);
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io.dpath.mem_load := mem_reg_mem_val && ((mem_reg_mem_cmd === M_XRD) || mem_reg_mem_cmd(3).toBool);
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io.dpath.ren2 := id_ren2.toBool;
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io.dpath.ren2 := id_ren2.toBool;
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io.dpath.ren1 := id_ren1.toBool;
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io.dpath.ren1 := id_ren1.toBool;
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io.dpath.sel_alu2 := id_sel_alu2;
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io.dpath.sel_alu2 := id_sel_alu2;
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@ -64,7 +64,7 @@ class rocketDTLB(entries: Int) extends Component
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val req_load = (r_cpu_req_cmd === M_XRD);
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val req_load = (r_cpu_req_cmd === M_XRD);
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val req_store = (r_cpu_req_cmd === M_XWR);
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val req_store = (r_cpu_req_cmd === M_XWR);
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val req_flush = (r_cpu_req_cmd === M_FLA);
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val req_flush = (r_cpu_req_cmd === M_FLA);
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// val req_amo = io.cpu.req_cmd(3).toBool;
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val req_amo = io.cpu.req_cmd(3).toBool;
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val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn);
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val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn);
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@ -139,20 +139,20 @@ class rocketDTLB(entries: Int) extends Component
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val outofrange = !tlb_miss && (io.cpu.resp_ppn > UFix(MEMSIZE_PAGES, PPN_BITS));
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val outofrange = !tlb_miss && (io.cpu.resp_ppn > UFix(MEMSIZE_PAGES, PPN_BITS));
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val access_fault_ld =
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val access_fault_ld =
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tlb_hit && req_load &&
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tlb_hit && (req_load || req_amo) &&
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((status_s && !sr_array(tag_hit_addr).toBool) ||
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((status_s && !sr_array(tag_hit_addr).toBool) ||
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(status_u && !ur_array(tag_hit_addr).toBool));
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(status_u && !ur_array(tag_hit_addr).toBool));
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io.cpu.xcpt_ld :=
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io.cpu.xcpt_ld :=
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(lookup && req_load && outofrange) || access_fault_ld;
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(lookup && (req_load || req_amo) && outofrange) || access_fault_ld;
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val access_fault_st =
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val access_fault_st =
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tlb_hit && req_store &&
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tlb_hit && (req_store || req_amo) &&
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((status_s && !sw_array(tag_hit_addr).toBool) ||
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((status_s && !sw_array(tag_hit_addr).toBool) ||
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(status_u && !uw_array(tag_hit_addr).toBool));
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(status_u && !uw_array(tag_hit_addr).toBool));
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io.cpu.xcpt_st :=
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io.cpu.xcpt_st :=
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(lookup && req_store && outofrange) || access_fault_st;
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(lookup && (req_store || req_amo) && outofrange) || access_fault_st;
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io.cpu.req_rdy := Mux(status_vm, (state === s_ready) && !tlb_miss, Bool(true));
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io.cpu.req_rdy := Mux(status_vm, (state === s_ready) && !tlb_miss, Bool(true));
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io.cpu.resp_busy := tlb_miss || (state != s_ready);
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io.cpu.resp_busy := tlb_miss || (state != s_ready);
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