riscv/rocket-chip
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more amo fixes, added more options to testharness to control debug messages

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This commit is contained in:
Rimas Avizienis 2011-11-15 02:43:51 -08:00
parent 82a636ff55
commit ae98956e6b
2 changed files with 9 additions and 8 deletions
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7
rocket/src/main/scala/ctrl.scala
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@ -570,8 +570,9 @@ class rocketCtrl extends Component
io.dpath.stalld io.dpath.stalld
); );
// check for loads in execute and mem stages to detect load/use hazards // check for loads and amos in execute and mem stages to detect load/use hazards
val ex_mem_cmd_load = ex_reg_mem_val && (ex_reg_mem_cmd === M_XRD); val ex_mem_cmd_load =
ex_reg_mem_val && ((ex_reg_mem_cmd === M_XRD) || ex_reg_mem_cmd(3).toBool);
val lu_stall_ex = val lu_stall_ex =
ex_mem_cmd_load && ex_mem_cmd_load &&
@ -643,7 +644,7 @@ class rocketCtrl extends Component
io.dpath.killx := kill_ex.toBool; io.dpath.killx := kill_ex.toBool;
io.dpath.killm := kill_mem.toBool; io.dpath.killm := kill_mem.toBool;
io.dpath.mem_load := mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD); io.dpath.mem_load := mem_reg_mem_val && ((mem_reg_mem_cmd === M_XRD) || mem_reg_mem_cmd(3).toBool);
io.dpath.ren2 := id_ren2.toBool; io.dpath.ren2 := id_ren2.toBool;
io.dpath.ren1 := id_ren1.toBool; io.dpath.ren1 := id_ren1.toBool;
io.dpath.sel_alu2 := id_sel_alu2; io.dpath.sel_alu2 := id_sel_alu2;

10
rocket/src/main/scala/dtlb.scala
View File

@ -64,7 +64,7 @@ class rocketDTLB(entries: Int) extends Component
val req_load = (r_cpu_req_cmd === M_XRD); val req_load = (r_cpu_req_cmd === M_XRD);
val req_store = (r_cpu_req_cmd === M_XWR); val req_store = (r_cpu_req_cmd === M_XWR);
val req_flush = (r_cpu_req_cmd === M_FLA); val req_flush = (r_cpu_req_cmd === M_FLA);
// val req_amo = io.cpu.req_cmd(3).toBool; val req_amo = io.cpu.req_cmd(3).toBool;
val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn); val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn);
@ -139,20 +139,20 @@ class rocketDTLB(entries: Int) extends Component
val outofrange = !tlb_miss && (io.cpu.resp_ppn > UFix(MEMSIZE_PAGES, PPN_BITS)); val outofrange = !tlb_miss && (io.cpu.resp_ppn > UFix(MEMSIZE_PAGES, PPN_BITS));
val access_fault_ld = val access_fault_ld =
tlb_hit && req_load && tlb_hit && (req_load || req_amo) &&
((status_s && !sr_array(tag_hit_addr).toBool) || ((status_s && !sr_array(tag_hit_addr).toBool) ||
(status_u && !ur_array(tag_hit_addr).toBool)); (status_u && !ur_array(tag_hit_addr).toBool));
io.cpu.xcpt_ld := io.cpu.xcpt_ld :=
(lookup && req_load && outofrange) || access_fault_ld; (lookup && (req_load || req_amo) && outofrange) || access_fault_ld;
val access_fault_st = val access_fault_st =
tlb_hit && req_store && tlb_hit && (req_store || req_amo) &&
((status_s && !sw_array(tag_hit_addr).toBool) || ((status_s && !sw_array(tag_hit_addr).toBool) ||
(status_u && !uw_array(tag_hit_addr).toBool)); (status_u && !uw_array(tag_hit_addr).toBool));
io.cpu.xcpt_st := io.cpu.xcpt_st :=
(lookup && req_store && outofrange) || access_fault_st; (lookup && (req_store || req_amo) && outofrange) || access_fault_st;
io.cpu.req_rdy := Mux(status_vm, (state === s_ready) && !tlb_miss, Bool(true)); io.cpu.req_rdy := Mux(status_vm, (state === s_ready) && !tlb_miss, Bool(true));
io.cpu.resp_busy := tlb_miss || (state != s_ready); io.cpu.resp_busy := tlb_miss || (state != s_ready);