riscv/rocket-chip
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more amo fixes, added more options to testharness to control debug messages

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This commit is contained in:
Rimas Avizienis
2011-11-15 02:43:51 -08:00
parent 82a636ff55
commit ae98956e6b
2 changed files with 9 additions and 8 deletions
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7
rocket/src/main/scala/ctrl.scala
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@ -570,8 +570,9 @@ class rocketCtrl extends Component
io.dpath.stalld
);
// check for loads in execute and mem stages to detect load/use hazards
val ex_mem_cmd_load = ex_reg_mem_val && (ex_reg_mem_cmd === M_XRD);
// check for loads and amos in execute and mem stages to detect load/use hazards
val ex_mem_cmd_load =
ex_reg_mem_val && ((ex_reg_mem_cmd === M_XRD) || ex_reg_mem_cmd(3).toBool);
val lu_stall_ex =
ex_mem_cmd_load &&
@ -643,7 +644,7 @@ class rocketCtrl extends Component
io.dpath.killx := kill_ex.toBool;
io.dpath.killm := kill_mem.toBool;
io.dpath.mem_load := mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD);
io.dpath.mem_load := mem_reg_mem_val && ((mem_reg_mem_cmd === M_XRD) || mem_reg_mem_cmd(3).toBool);
io.dpath.ren2 := id_ren2.toBool;
io.dpath.ren1 := id_ren1.toBool;
io.dpath.sel_alu2 := id_sel_alu2;